/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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The request crossbar in the VC allocator of VC routers.
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The request crossbar in the VC allocator of VC routers.
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History:
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History:
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04/04/2010 Initial version. <wsong83@gmail.com>
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04/04/2010 Initial version. <wsong83@gmail.com>
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01/06/2011 Clean up for opensource. <wsong83@gmail.com>
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01/06/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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module rcb_vc (/*AUTOARG*/
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module rcb_vc (/*AUTOARG*/
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// Outputs
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// Outputs
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ro, srt, nrt, lrt, wrt, ert, wctla, ectla, lctla, sctla, nctla,
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ro, srt, nrt, lrt, wrt, ert, wctla, ectla, lctla, sctla, nctla,
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// Inputs
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// Inputs
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ri, go, wctl, ectl, lctl, sctl, nctl
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ri, go, wctl, ectl, lctl, sctl, nctl
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);
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);
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parameter VCN = 2; // the number of VCs per direction
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parameter VCN = 2; // the number of VCs per direction
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input [4:0][VCN-1:0][1:0] ri; // the request input from all inputs
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input [4:0][VCN-1:0][1:0] ri; // the request input from all inputs
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output [4:0][VCN-1:0] ro; // the request output to all output port arbiters
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output [4:0][VCN-1:0] ro; // the request output to all output port arbiters
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input [4:0][VCN-1:0] go; // the granted VC info from all output port arbiters
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input [4:0][VCN-1:0] go; // the granted VC info from all output port arbiters
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output [VCN-1:0][3:0] srt, nrt, lrt; // routing guide to all input ports
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output [VCN-1:0][3:0] srt, nrt, lrt; // routing guide to all input ports
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output [VCN-1:0][1:0] wrt, ert;
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output [VCN-1:0][1:0] wrt, ert;
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input [VCN*4*VCN-1:0] wctl, ectl, lctl; // the configuration from VCA
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input [VCN*4*VCN-1:0] wctl, ectl, lctl; // the configuration from VCA
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input [VCN*2*VCN-1:0] sctl, nctl;
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input [VCN*2*VCN-1:0] sctl, nctl;
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output [VCN*4*VCN-1:0] wctla, ectla, lctla; // the ack to VCA, fire when the frame is sent
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output [VCN*4*VCN-1:0] wctla, ectla, lctla; // the ack to VCA, fire when the frame is sent
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output [VCN*2*VCN-1:0] sctla, nctla;
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output [VCN*2*VCN-1:0] sctla, nctla;
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wire [VCN*4*VCN-1:0][1:0] wri, eri, lri;
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wire [VCN*4*VCN-1:0][1:0] wri, eri, lri;
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wire [VCN*4*VCN-1:0] wgi, wgo, wro, egi, ego, ero, lgi, lgo, lro;
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wire [VCN*4*VCN-1:0] wgi, wgo, wro, egi, ego, ero, lgi, lgo, lro;
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wire [VCN*2*VCN-1:0][1:0] sri, nri;
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wire [VCN*2*VCN-1:0][1:0] sri, nri;
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wire [VCN*2*VCN-1:0] sgi, sgo, sro, ngi, ngo, nro;
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wire [VCN*2*VCN-1:0] sgi, sgo, sro, ngi, ngo, nro;
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wire [4*VCN*VCN-1:0] wgis, egis, lgis;
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wire [4*VCN*VCN-1:0] wgis, egis, lgis;
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wire [2*VCN*VCN-1:0] sgis, ngis;
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wire [2*VCN*VCN-1:0] sgis, ngis;
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genvar i,j;
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genvar i,j;
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generate
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generate
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for(i=0; i<VCN; i++) begin:RI
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for(i=0; i<VCN; i++) begin:RI
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// shuffle the input requests to all output ports
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// shuffle the input requests to all output ports
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for(j=0; j<VCN; j++) begin: J
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for(j=0; j<VCN; j++) begin: J
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assign sri[i*2*VCN+0*VCN+j] = ri[2][j];
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assign sri[i*2*VCN+0*VCN+j] = ri[2][j];
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assign sri[i*2*VCN+1*VCN+j] = ri[4][j];
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assign sri[i*2*VCN+1*VCN+j] = ri[4][j];
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assign wri[i*4*VCN+0*VCN+j] = ri[0][j];
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assign wri[i*4*VCN+0*VCN+j] = ri[0][j];
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assign wri[i*4*VCN+1*VCN+j] = ri[2][j];
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assign wri[i*4*VCN+1*VCN+j] = ri[2][j];
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assign wri[i*4*VCN+2*VCN+j] = ri[3][j];
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assign wri[i*4*VCN+2*VCN+j] = ri[3][j];
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assign wri[i*4*VCN+3*VCN+j] = ri[4][j];
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assign wri[i*4*VCN+3*VCN+j] = ri[4][j];
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assign nri[i*2*VCN+0*VCN+j] = ri[0][j];
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assign nri[i*2*VCN+0*VCN+j] = ri[0][j];
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assign nri[i*2*VCN+1*VCN+j] = ri[4][j];
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assign nri[i*2*VCN+1*VCN+j] = ri[4][j];
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assign eri[i*4*VCN+0*VCN+j] = ri[0][j];
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assign eri[i*4*VCN+0*VCN+j] = ri[0][j];
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assign eri[i*4*VCN+1*VCN+j] = ri[1][j];
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assign eri[i*4*VCN+1*VCN+j] = ri[1][j];
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assign eri[i*4*VCN+2*VCN+j] = ri[2][j];
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assign eri[i*4*VCN+2*VCN+j] = ri[2][j];
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assign eri[i*4*VCN+3*VCN+j] = ri[4][j];
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assign eri[i*4*VCN+3*VCN+j] = ri[4][j];
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assign lri[i*4*VCN+0*VCN+j] = ri[0][j];
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assign lri[i*4*VCN+0*VCN+j] = ri[0][j];
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assign lri[i*4*VCN+1*VCN+j] = ri[1][j];
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assign lri[i*4*VCN+1*VCN+j] = ri[1][j];
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assign lri[i*4*VCN+2*VCN+j] = ri[2][j];
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assign lri[i*4*VCN+2*VCN+j] = ri[2][j];
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assign lri[i*4*VCN+3*VCN+j] = ri[3][j];
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assign lri[i*4*VCN+3*VCN+j] = ri[3][j];
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end
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end
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// generate the requests to output port arbiters
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// generate the requests to output port arbiters
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assign ro[0][i] = |sro[i*2*VCN +: 2*VCN];
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assign ro[0][i] = |sro[i*2*VCN +: 2*VCN];
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assign ro[1][i] = |wro[i*4*VCN +: 4*VCN];
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assign ro[1][i] = |wro[i*4*VCN +: 4*VCN];
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assign ro[2][i] = |nro[i*2*VCN +: 2*VCN];
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assign ro[2][i] = |nro[i*2*VCN +: 2*VCN];
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assign ro[3][i] = |ero[i*4*VCN +: 4*VCN];
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assign ro[3][i] = |ero[i*4*VCN +: 4*VCN];
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assign ro[4][i] = |lro[i*4*VCN +: 4*VCN];
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assign ro[4][i] = |lro[i*4*VCN +: 4*VCN];
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// demux to duplicate the grant to all input ports
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// demux to duplicate the grant to all input ports
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assign sgo[i*2*VCN +: 2*VCN] = {2*VCN{go[0][i]}};
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assign sgo[i*2*VCN +: 2*VCN] = {2*VCN{go[0][i]}};
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assign wgo[i*4*VCN +: 4*VCN] = {4*VCN{go[1][i]}};
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assign wgo[i*4*VCN +: 4*VCN] = {4*VCN{go[1][i]}};
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assign ngo[i*2*VCN +: 2*VCN] = {2*VCN{go[2][i]}};
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assign ngo[i*2*VCN +: 2*VCN] = {2*VCN{go[2][i]}};
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assign ego[i*4*VCN +: 4*VCN] = {4*VCN{go[3][i]}};
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assign ego[i*4*VCN +: 4*VCN] = {4*VCN{go[3][i]}};
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assign lgo[i*4*VCN +: 4*VCN] = {4*VCN{go[4][i]}};
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assign lgo[i*4*VCN +: 4*VCN] = {4*VCN{go[4][i]}};
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// generate the routing guide from output grants (sgo -- lgo)
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// generate the routing guide from output grants (sgo -- lgo)
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assign srt[i] = {|lgis[(0*VCN+i)*VCN +: VCN], |egis[(0*VCN+i)*VCN +: VCN], |ngis[(0*VCN+i)*VCN +: VCN], |wgis[(0*VCN+i)*VCN +: VCN]};
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assign srt[i] = {|lgis[(0*VCN+i)*VCN +: VCN], |egis[(0*VCN+i)*VCN +: VCN], |ngis[(0*VCN+i)*VCN +: VCN], |wgis[(0*VCN+i)*VCN +: VCN]};
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assign wrt[i] = {|lgis[(1*VCN+i)*VCN +: VCN], |egis[(1*VCN+i)*VCN +: VCN]};
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assign wrt[i] = {|lgis[(1*VCN+i)*VCN +: VCN], |egis[(1*VCN+i)*VCN +: VCN]};
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assign nrt[i] = {|lgis[(2*VCN+i)*VCN +: VCN], |egis[(2*VCN+i)*VCN +: VCN], |wgis[(1*VCN+i)*VCN +: VCN], |sgis[(0*VCN+i)*VCN +: VCN]};
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assign nrt[i] = {|lgis[(2*VCN+i)*VCN +: VCN], |egis[(2*VCN+i)*VCN +: VCN], |wgis[(1*VCN+i)*VCN +: VCN], |sgis[(0*VCN+i)*VCN +: VCN]};
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assign ert[i] = {|lgis[(3*VCN+i)*VCN +: VCN], |wgis[(2*VCN+i)*VCN +: VCN]};
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assign ert[i] = {|lgis[(3*VCN+i)*VCN +: VCN], |wgis[(2*VCN+i)*VCN +: VCN]};
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assign lrt[i] = {|egis[(3*VCN+i)*VCN +: VCN], |ngis[(1*VCN+i)*VCN +: VCN], |wgis[(3*VCN+i)*VCN +: VCN], |sgis[(1*VCN+i)*VCN +: VCN]};
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assign lrt[i] = {|egis[(3*VCN+i)*VCN +: VCN], |ngis[(1*VCN+i)*VCN +: VCN], |wgis[(3*VCN+i)*VCN +: VCN], |sgis[(1*VCN+i)*VCN +: VCN]};
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// part of the routing guide process
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// part of the routing guide process
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for(j=0; j<4*VCN; j++) begin:SB
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for(j=0; j<4*VCN; j++) begin:SB
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assign wgis[j*VCN+i] = wgi[i*4*VCN+j];
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assign wgis[j*VCN+i] = wgi[i*4*VCN+j];
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assign egis[j*VCN+i] = egi[i*4*VCN+j];
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assign egis[j*VCN+i] = egi[i*4*VCN+j];
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assign lgis[j*VCN+i] = lgi[i*4*VCN+j];
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assign lgis[j*VCN+i] = lgi[i*4*VCN+j];
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end
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end
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for(j=0; j<2*VCN; j++) begin:SL
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for(j=0; j<2*VCN; j++) begin:SL
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assign sgis[j*VCN+i] = sgi[i*2*VCN+j];
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assign sgis[j*VCN+i] = sgi[i*2*VCN+j];
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assign ngis[j*VCN+i] = ngi[i*2*VCN+j];
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assign ngis[j*VCN+i] = ngi[i*2*VCN+j];
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end
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end
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end
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end
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// cross points
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// cross points
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for(i=0; i<VCN*4*VCN; i++) begin:BB
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for(i=0; i<VCN*4*VCN; i++) begin:BB
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RCBB W (.ri(wri[i]), .ro(wro[i]), .go(wgo[i]), .gi(wgi[i]), .ctl(wctl[i]), .ctla(wctla[i]));
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RCBB W (.ri(wri[i]), .ro(wro[i]), .go(wgo[i]), .gi(wgi[i]), .ctl(wctl[i]), .ctla(wctla[i]));
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RCBB E (.ri(eri[i]), .ro(ero[i]), .go(ego[i]), .gi(egi[i]), .ctl(ectl[i]), .ctla(ectla[i]));
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RCBB E (.ri(eri[i]), .ro(ero[i]), .go(ego[i]), .gi(egi[i]), .ctl(ectl[i]), .ctla(ectla[i]));
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RCBB L (.ri(lri[i]), .ro(lro[i]), .go(lgo[i]), .gi(lgi[i]), .ctl(lctl[i]), .ctla(lctla[i]));
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RCBB L (.ri(lri[i]), .ro(lro[i]), .go(lgo[i]), .gi(lgi[i]), .ctl(lctl[i]), .ctla(lctla[i]));
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end
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end
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for(i=0; i<VCN*2*VCN; i++) begin:BL
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for(i=0; i<VCN*2*VCN; i++) begin:BL
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RCBB S (.ri(sri[i]), .ro(sro[i]), .go(sgo[i]), .gi(sgi[i]), .ctl(sctl[i]), .ctla(sctla[i]));
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RCBB S (.ri(sri[i]), .ro(sro[i]), .go(sgo[i]), .gi(sgi[i]), .ctl(sctl[i]), .ctla(sctla[i]));
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RCBB N (.ri(nri[i]), .ro(nro[i]), .go(ngo[i]), .gi(ngi[i]), .ctl(nctl[i]), .ctla(nctla[i]));
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RCBB N (.ri(nri[i]), .ro(nro[i]), .go(ngo[i]), .gi(ngi[i]), .ctl(nctl[i]), .ctla(nctla[i]));
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end
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end
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endgenerate
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endgenerate
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endmodule // rcb_vc
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endmodule // rcb_vc
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// Request CrossBar cross point Block
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// Request CrossBar cross point Block
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module RCBB (ri, ro, go, gi, ctl, ctla);
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module RCBB (ri, ro, go, gi, ctl, ctla);
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input [1:0] ri; // requests from input ports (0: data and head, 1: eof)
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input [1:0] ri; // requests from input ports (0: data and head, 1: eof)
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output ro; // requests to output ports
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output ro; // requests to output ports
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input go; // grant from output ports
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input go; // grant from output ports
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output gi; // grant to input ports, later translated into routing guide
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output gi; // grant to input ports, later translated into routing guide
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input ctl; // configuration from VCA
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input ctl; // configuration from VCA
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output ctla; // configuration ack to VCA, fire after ri[1] fires
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output ctla; // configuration ack to VCA, fire after ri[1] fires
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wire [1:0] m;
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wire [1:0] m;
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c2 I0 (.a0(ri[1]), .a1(ctl), .q(m[1]));
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c2 I0 (.a0(ri[1]), .a1(ctl), .q(m[1]));
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and I1 ( m[0], ri[0], ctl);
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and I1 ( m[0], ri[0], ctl);
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or I2 ( ro, m[0], m[1]);
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or I2 ( ro, m[0], m[1]);
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c2 I3 ( .a0(ro), .a1(go), .q(gi));
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c2 I3 ( .a0(ro), .a1(go), .q(gi));
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c2 IA ( .a0(m[1]), .a1(go), .q(ctla));
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c2 IA ( .a0(m[1]), .a1(go), .q(ctla));
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endmodule // RCBB
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endmodule // RCBB
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