/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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Demux for a VC buffer stage.
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Demux for a VC buffer stage.
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History:
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History:
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31/03/2010 Initial version. <wsong83@gmail.com>
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31/03/2010 Initial version. <wsong83@gmail.com>
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02/06/2011 Clean up for opensource. <wsong83@gmail.com>
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02/06/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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module vcdmux ( /*AUTOARG*/
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module vcdmux ( /*AUTOARG*/
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// Outputs
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// Outputs
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dia, do0, do1, do2, do3, dot,
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dia, do0, do1, do2, do3, dot,
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// Inputs
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// Inputs
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di0, di1, di2, di3, dit, divc, doa
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di0, di1, di2, di3, dit, divc, doa
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);
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);
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parameter VCN = 2; // number of output VCs
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parameter VCN = 2; // number of output VCs
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parameter DW = 32; // data width of the input
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parameter DW = 32; // data width of the input
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parameter SCN = DW/2;
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parameter SCN = DW/2;
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input [SCN-1:0] di0, di1, di2, di3;
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input [SCN-1:0] di0, di1, di2, di3;
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input [2:0] dit;
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input [2:0] dit;
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input [VCN-1:0] divc;
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input [VCN-1:0] divc;
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output dia;
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output dia;
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output [VCN-1:0][SCN-1:0] do0, do1, do2, do3;
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output [VCN-1:0][SCN-1:0] do0, do1, do2, do3;
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output [VCN-1:0][2:0] dot;
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output [VCN-1:0][2:0] dot;
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input [VCN-1:0] doa;
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input [VCN-1:0] doa;
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genvar i,j;
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genvar i,j;
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/*
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/*
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generate
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generate
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for (i=0; i<VCN; i++) begin: VCD
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for (i=0; i<VCN; i++) begin: VCD
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for(j=0; j<SCN; j++) begin: D
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for(j=0; j<SCN; j++) begin: D
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c2 C0 (.a0(di0[j]), .a1(divc[i]), .q(do0[i][j]));
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c2 C0 (.a0(di0[j]), .a1(divc[i]), .q(do0[i][j]));
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c2 C1 (.a0(di1[j]), .a1(divc[i]), .q(do1[i][j]));
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c2 C1 (.a0(di1[j]), .a1(divc[i]), .q(do1[i][j]));
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c2 C2 (.a0(di2[j]), .a1(divc[i]), .q(do2[i][j]));
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c2 C2 (.a0(di2[j]), .a1(divc[i]), .q(do2[i][j]));
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c2 C3 (.a0(di3[j]), .a1(divc[i]), .q(do3[i][j]));
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c2 C3 (.a0(di3[j]), .a1(divc[i]), .q(do3[i][j]));
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end
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end
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for(j=0; j<3; j++) begin: T
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for(j=0; j<3; j++) begin: T
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c2 C0 (.a0(dit[j]), .a1(divc[i]), .q(dot[i][j]));
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c2 C0 (.a0(dit[j]), .a1(divc[i]), .q(dot[i][j]));
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end
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end
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end
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end
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endgenerate
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endgenerate
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*/
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*/
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generate
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generate
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for (i=0; i<VCN; i++) begin: VCD
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for (i=0; i<VCN; i++) begin: VCD
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assign do0[i] = divc[i] ? di0 : 0;
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assign do0[i] = divc[i] ? di0 : 0;
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assign do1[i] = divc[i] ? di1 : 0;
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assign do1[i] = divc[i] ? di1 : 0;
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assign do2[i] = divc[i] ? di2 : 0;
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assign do2[i] = divc[i] ? di2 : 0;
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assign do3[i] = divc[i] ? di3 : 0;
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assign do3[i] = divc[i] ? di3 : 0;
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assign dot[i] = divc[i] ? dit : 0;
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assign dot[i] = divc[i] ? dit : 0;
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end
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end
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endgenerate
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endgenerate
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assign dia = |doa;
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assign dia = |doa;
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endmodule // vcdmux
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endmodule // vcdmux
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