/*
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/*
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Asynchronous SDM NoC
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Asynchronous SDM NoC
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(C)2011 Wei Song
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Authors:
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Wei Song wsong83@gmail.com
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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License: LGPL 3.0 or later
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The SystemC module of network node including the processing element and the network interface.
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The SystemC module of network node including the processing element and the network interface.
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Currently the transmission FIFO is 500 frame deep.
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Currently the transmission FIFO is 500 frame deep.
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History:
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History:
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26/02/2011 Initial version. <wsong83@gmail.com>
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26/02/2011 Initial version. <wsong83@gmail.com>
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04/03/2011 Support VC router. <wsong83@gmail.com>
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04/03/2011 Support VC router. <wsong83@gmail.com>
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05/06/2011 Clean up for opensource. <wsong83@gmail.com>
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05/06/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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#ifndef NETNODE_H_
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#ifndef NETNODE_H_
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#define NETNODE_H_
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#define NETNODE_H_
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#include "define.h"
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#include "define.h"
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#include <systemc.h>
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#include <systemc.h>
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#include "ni.h"
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#include "ni.h"
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#include "procelem.h"
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#include "procelem.h"
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#include "rtdriver.h"
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#include "rtdriver.h"
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class NetNode : public sc_module {
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class NetNode : public sc_module {
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public:
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public:
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RTDriver * LIOD; /* driving and convert I/O to/from router local port */
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RTDriver * LIOD; /* driving and convert I/O to/from router local port */
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Network_Adapter * NI; /* network interface */
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Network_Adapter * NI; /* network interface */
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ProcElem * PE; /* processor element */
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ProcElem * PE; /* processor element */
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// signals for router
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// signals for router
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sc_out< sc_logic > doa ;
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sc_out< sc_logic > doa ;
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sc_out< sc_lv<SubChN > > doc ;
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sc_out< sc_lv<SubChN > > doc ;
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sc_in< sc_lv<ChBW*4 > > do0 ;
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sc_in< sc_lv<ChBW*4 > > do0 ;
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sc_in< sc_lv<ChBW*4 > > do1 ;
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sc_in< sc_lv<ChBW*4 > > do1 ;
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sc_in< sc_lv<ChBW*4 > > do2 ;
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sc_in< sc_lv<ChBW*4 > > do2 ;
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sc_in< sc_lv<ChBW*4 > > do3 ;
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sc_in< sc_lv<ChBW*4 > > do3 ;
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sc_in< sc_lv<3> > doft;
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sc_in< sc_lv<3> > doft;
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sc_in< sc_lv<SubChN > > dovc;
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sc_in< sc_lv<SubChN > > dovc;
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sc_in< sc_lv<SubChN > > doca;
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sc_in< sc_lv<SubChN > > doca;
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sc_in< sc_logic > dia;
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sc_in< sc_logic > dia;
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sc_in< sc_lv<SubChN > > dic;
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sc_in< sc_lv<SubChN > > dic;
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sc_out< sc_lv<ChBW*4 > > di0;
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sc_out< sc_lv<ChBW*4 > > di0;
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sc_out< sc_lv<ChBW*4 > > di1;
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sc_out< sc_lv<ChBW*4 > > di1;
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sc_out< sc_lv<ChBW*4 > > di2;
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sc_out< sc_lv<ChBW*4 > > di2;
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sc_out< sc_lv<ChBW*4 > > di3;
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sc_out< sc_lv<ChBW*4 > > di3;
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sc_out< sc_lv<3> > dift;
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sc_out< sc_lv<3> > dift;
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sc_out< sc_lv<SubChN > > divc;
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sc_out< sc_lv<SubChN > > divc;
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sc_out< sc_lv<SubChN > > dica;
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sc_out< sc_lv<SubChN > > dica;
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sc_in<sc_logic > rst_n; /* global active-low reset */
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sc_in<sc_logic > rst_n; /* global active-low reset */
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// signals between IOD and NI
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// signals between IOD and NI
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sc_fifo<pdu_flit<ChBW> > * NI2P ; /* flit fifo, from NI to IO driver */
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sc_fifo<pdu_flit<ChBW> > * NI2P ; /* flit fifo, from NI to IO driver */
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sc_fifo<pdu_flit<ChBW> > * P2NI ; /* flit fifo, from IO driver to NI */
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sc_fifo<pdu_flit<ChBW> > * P2NI ; /* flit fifo, from IO driver to NI */
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sc_signal<bool> CP [SubChN]; /* credit input */
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sc_signal<bool> CP [SubChN]; /* credit input */
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sc_signal<bool> CPa [SubChN]; /* credit ack */
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sc_signal<bool> CPa [SubChN]; /* credit ack */
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// signals between NI and FG/FS
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// signals between NI and FG/FS
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sc_fifo<pdu_frame<ChBW> > * FIQ; /* the frame fifo, from PE to NI */
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sc_fifo<pdu_frame<ChBW> > * FIQ; /* the frame fifo, from PE to NI */
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sc_fifo<pdu_frame<ChBW> > * FOQ; /* the frame fifo, from NI to PE */
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sc_fifo<pdu_frame<ChBW> > * FOQ; /* the frame fifo, from NI to PE */
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sc_signal<bool> brst_n; /* the reset in the SystemC modules */
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sc_signal<bool> brst_n; /* the reset in the SystemC modules */
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int x, y; /* private local address */
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int x, y; /* private local address */
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SC_CTOR(NetNode)
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SC_CTOR(NetNode)
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: doa("doa"), doc("doc"),
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: doa("doa"), doc("doc"),
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do0("do0"), do1("do1"), do2("do2"), do3("do3"),
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do0("do0"), do1("do1"), do2("do2"), do3("do3"),
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doft("doft"), dovc("dovc"), doca("doca"),
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doft("doft"), dovc("dovc"), doca("doca"),
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dia("dia"), dic("dic"),
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dia("dia"), dic("dic"),
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di0("di0"), di1("di1"), di2("di2"), di3("di3"),
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di0("di0"), di1("di1"), di2("di2"), di3("di3"),
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dift("dift"), divc("divc"), dica("dica"),
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dift("dift"), divc("divc"), dica("dica"),
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rst_n("rst_n")
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rst_n("rst_n")
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{
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{
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// dynamically get the parameters from Verilog test bench
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// dynamically get the parameters from Verilog test bench
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ncsc_get_param("x", x);
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ncsc_get_param("x", x);
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ncsc_get_param("y", y);
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ncsc_get_param("y", y);
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// initialization
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// initialization
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LIOD = new RTDriver("LIOD");
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LIOD = new RTDriver("LIOD");
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NI = new Network_Adapter("NI", x, y);
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NI = new Network_Adapter("NI", x, y);
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PE = new ProcElem("PE", x, y);
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PE = new ProcElem("PE", x, y);
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NI2P = new sc_fifo<pdu_flit<ChBW> >(1);
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NI2P = new sc_fifo<pdu_flit<ChBW> >(1);
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P2NI = new sc_fifo<pdu_flit<ChBW> >(1);
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P2NI = new sc_fifo<pdu_flit<ChBW> >(1);
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FIQ = new sc_fifo<pdu_frame<ChBW> >(500);/* currently the fifo from PE is 500 frame deep */
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FIQ = new sc_fifo<pdu_frame<ChBW> >(500);/* currently the fifo from PE is 500 frame deep */
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FOQ = new sc_fifo<pdu_frame<ChBW> >(1);
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FOQ = new sc_fifo<pdu_frame<ChBW> >(1);
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// connections
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// connections
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LIOD->NI2P(*NI2P);
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LIOD->NI2P(*NI2P);
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LIOD->P2NI(*P2NI);
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LIOD->P2NI(*P2NI);
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LIOD->rtid[0](di0);
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LIOD->rtid[0](di0);
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LIOD->rtod[0](do0);
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LIOD->rtod[0](do0);
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LIOD->rtid[1](di1);
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LIOD->rtid[1](di1);
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LIOD->rtod[1](do1);
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LIOD->rtod[1](do1);
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LIOD->rtid[2](di2);
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LIOD->rtid[2](di2);
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LIOD->rtod[2](do2);
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LIOD->rtod[2](do2);
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LIOD->rtid[3](di3);
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LIOD->rtid[3](di3);
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LIOD->rtod[3](do3);
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LIOD->rtod[3](do3);
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LIOD->rtift(dift);
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LIOD->rtift(dift);
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LIOD->rtivc(divc);
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LIOD->rtivc(divc);
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LIOD->rtia(dia);
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LIOD->rtia(dia);
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LIOD->rtic(dic);
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LIOD->rtic(dic);
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LIOD->rtica(dica);
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LIOD->rtica(dica);
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LIOD->rtoft(doft);
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LIOD->rtoft(doft);
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LIOD->rtovc(dovc);
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LIOD->rtovc(dovc);
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LIOD->rtoa(doa);
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LIOD->rtoa(doa);
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LIOD->rtoc(doc);
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LIOD->rtoc(doc);
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LIOD->rtoca(doca);
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LIOD->rtoca(doca);
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for(unsigned int j=0; j<SubChN; j++) {
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for(unsigned int j=0; j<SubChN; j++) {
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LIOD->CP[j](CP[j]);
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LIOD->CP[j](CP[j]);
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LIOD->CPa[j](CPa[j]);
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LIOD->CPa[j](CPa[j]);
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}
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}
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NI->frame_in(*FIQ);
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NI->frame_in(*FIQ);
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NI->frame_out(*FOQ);
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NI->frame_out(*FOQ);
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NI->IP(*P2NI);
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NI->IP(*P2NI);
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NI->OP(*NI2P);
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NI->OP(*NI2P);
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for(unsigned int j=0; j<SubChN; j++) {
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for(unsigned int j=0; j<SubChN; j++) {
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NI->CP[j](CP[j]);
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NI->CP[j](CP[j]);
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NI->CPa[j](CPa[j]);
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NI->CPa[j](CPa[j]);
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}
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}
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PE->rst_n(brst_n);
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PE->rst_n(brst_n);
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PE->Fout(*FIQ);
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PE->Fout(*FIQ);
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PE->Fin(*FOQ);
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PE->Fin(*FOQ);
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brst_n.write(false);
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brst_n.write(false);
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SC_METHOD(rst_proc);
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SC_METHOD(rst_proc);
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sensitive << rst_n;
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sensitive << rst_n;
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}
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}
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void rst_proc() {
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void rst_proc() {
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bool mrst_n;
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bool mrst_n;
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mrst_n = rst_n.read().is_01() ? rst_n.read().to_bool() : false;
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mrst_n = rst_n.read().is_01() ? rst_n.read().to_bool() : false;
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brst_n.write(mrst_n);
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brst_n.write(mrst_n);
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}
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}
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};
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};
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#endif
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#endif
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