/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
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//// ATA (IDE) Device Model ////
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//// ATA (IDE) Device Model ////
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//// This Model Supports PIO cycles only ! ////
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//// This Model Supports PIO cycles only ! ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/ata/ ////
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//// Downloaded from: http://www.opencores.org/cores/ata/ ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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|
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// CVS Log
|
// CVS Log
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//
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//
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// $Id: ata_device.v,v 1.1 2001-08-16 10:01:05 rudi Exp $
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// $Id: ata_device.v,v 1.2 2002-02-25 06:07:21 rherveille Exp $
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//
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//
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// $Date: 2001-08-16 10:01:05 $
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// $Date: 2002-02-25 06:07:21 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/16 10:01:05 rudi
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//
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// - Added Test Bench
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// - Added Synthesis scripts for Design Compiler
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// - Fixed minor bug in atahost_top
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|
//
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//
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//
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//
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//
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//
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//
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//
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//
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`timescale 1ns / 10ps
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`timescale 1ns / 10ps
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module ata_device( ata_rst_, ata_data, ata_da, ata_cs0, ata_cs1,
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module ata_device( ata_rst_, ata_data, ata_da, ata_cs0, ata_cs1,
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ata_dior_, ata_diow_, ata_iordy, ata_intrq );
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ata_dior_, ata_diow_, ata_iordy, ata_intrq );
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input ata_rst_;
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input ata_rst_;
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inout [15:0] ata_data;
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inout [15:0] ata_data;
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input [2:0] ata_da;
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input [2:0] ata_da;
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input ata_cs0, ata_cs1;
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input ata_cs0, ata_cs1;
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input ata_dior_, ata_diow_;
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input ata_dior_, ata_diow_;
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output ata_iordy;
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output ata_iordy;
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output ata_intrq;
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output ata_intrq;
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integer mode;
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integer mode;
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integer n;
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integer n;
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reg ata_iordy;
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reg ata_iordy;
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reg iordy_enable;
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reg iordy_enable;
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integer iordy_delay;
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integer iordy_delay;
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reg [15:0] mem[32:0];
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reg [15:0] mem[32:0];
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reg [15:0] dout;
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reg [15:0] dout;
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reg dout_en;
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reg dout_en;
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wire ata_rst_m0, ata_rst_m1, ata_rst_m2, ata_rst_m3, ata_rst_m4;
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wire ata_rst_m0, ata_rst_m1, ata_rst_m2, ata_rst_m3, ata_rst_m4;
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wire [4:0] addr;
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wire [4:0] addr;
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wire ata_dior, ata_diow;
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wire ata_dior, ata_diow;
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|
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initial
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initial
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begin
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begin
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dout_en = 0;
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dout_en = 0;
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mode = 0;
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mode = 0;
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iordy_enable = 0;
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iordy_enable = 0;
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iordy_delay = 0;
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iordy_delay = 0;
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ata_iordy = 1;
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ata_iordy = 1;
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end
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end
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assign ata_dior = !ata_dior_;
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assign ata_dior = !ata_dior_;
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assign ata_diow = !ata_diow_;
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assign ata_diow = !ata_diow_;
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assign ata_intrq = 0;
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assign ata_intrq = 0;
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|
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assign ata_data = dout_en ? dout : 16'hzzzz;
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assign ata_data = dout_en ? dout : 16'hzzzz;
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assign addr = {~ata_cs1, ~ata_cs0, ata_da};
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assign addr = {~ata_cs1, ~ata_cs0, ata_da};
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always @(posedge ata_rst_)
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always @(posedge ata_rst_)
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dout_en = 0;
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dout_en = 0;
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always @(posedge ata_dior)
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always @(posedge ata_dior)
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begin
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begin
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dout = mem[ addr ];
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dout = mem[ addr ];
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dout_en = 1;
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dout_en = 1;
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end
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end
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always @(negedge ata_dior)
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always @(posedge ata_dior)
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begin
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begin
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dout_en = 0;
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dout_en = 0;
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end
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end
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always @(posedge ata_diow)
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always @(posedge ata_diow)
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begin
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begin
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mem[ addr ] = ata_data;
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mem[ addr ] = ata_data;
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end
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end
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always @(posedge ata_dior or posedge ata_diow)
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always @(posedge ata_dior or posedge ata_diow)
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begin
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begin
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ata_iordy = 1'b0;
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ata_iordy = 1'b0;
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#(iordy_delay);
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#(iordy_delay);
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ata_iordy = 1'b1;
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ata_iordy = 1'b1;
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end
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end
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task init_mem;
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task init_mem;
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|
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begin
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begin
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|
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for(n=0;n<32;n=n+1)
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for(n=0;n<32;n=n+1)
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mem[n] = n;
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mem[n] = n;
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end
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end
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endtask
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endtask
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assign ata_rst_m0 = ata_rst_ & (mode==0);
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assign ata_rst_m0 = ata_rst_ & (mode==0);
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assign ata_rst_m1 = ata_rst_ & (mode==1);
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assign ata_rst_m1 = ata_rst_ & (mode==1);
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assign ata_rst_m2 = ata_rst_ & (mode==2);
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assign ata_rst_m2 = ata_rst_ & (mode==2);
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assign ata_rst_m3 = ata_rst_ & (mode==3);
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assign ata_rst_m3 = ata_rst_ & (mode==3);
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assign ata_rst_m4 = ata_rst_ & (mode==4);
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assign ata_rst_m4 = ata_rst_ & (mode==4);
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specify
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specify
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specparam // ATA Mode 0 Timing
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specparam // ATA Mode 0 Timing
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M0_DioCycle = 600, // T0
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M0_DioCycle = 600, // T0
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M0_AddrSetup = 70, // T1
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M0_AddrSetup = 70, // T1
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M0_DioHigh = 290, // T2
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M0_DioHigh = 290, // T2
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M0_WrSetup = 60, // T3
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M0_WrSetup = 60, // T3
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M0_WrHold = 30, // T4
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M0_WrHold = 30, // T4
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M0_DoutSetup = 50, // T5
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M0_DoutSetup = 50, // T5
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M0_DoutHold = 5, // T6
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M0_DoutHold = 5, // T6
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M0_AddrHold = 20, // T9
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M0_AddrHold = 20, // T9
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// ATA Mode 1 Timing
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// ATA Mode 1 Timing
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M1_DioCycle = 383, // T0
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M1_DioCycle = 383, // T0
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M1_AddrSetup = 50, // T1
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M1_AddrSetup = 50, // T1
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M1_DioHigh = 290, // T2
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M1_DioHigh = 290, // T2
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M1_WrSetup = 45, // T3
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M1_WrSetup = 45, // T3
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M1_WrHold = 20, // T4
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M1_WrHold = 20, // T4
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M1_DoutSetup = 35, // T5
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M1_DoutSetup = 35, // T5
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M1_DoutHold = 5, // T6
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M1_DoutHold = 5, // T6
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M1_AddrHold = 15, // T9
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M1_AddrHold = 15, // T9
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// ATA Mode 2 Timing
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// ATA Mode 2 Timing
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M2_DioCycle = 330, // T0
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M2_DioCycle = 330, // T0
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M2_AddrSetup = 30, // T1
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M2_AddrSetup = 30, // T1
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M2_DioHigh = 290, // T2
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M2_DioHigh = 290, // T2
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M2_WrSetup = 30, // T3
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M2_WrSetup = 30, // T3
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M2_WrHold = 15, // T4
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M2_WrHold = 15, // T4
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M2_DoutSetup = 20, // T5
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M2_DoutSetup = 20, // T5
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M2_DoutHold = 5, // T6
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M2_DoutHold = 5, // T6
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M2_AddrHold = 10, // T9
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M2_AddrHold = 10, // T9
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// ATA Mode 3 Timing
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// ATA Mode 3 Timing
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M3_DioCycle = 180, // T0
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M3_DioCycle = 180, // T0
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M3_AddrSetup = 30, // T1
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M3_AddrSetup = 30, // T1
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M3_DioHigh = 80, // T2
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M3_DioHigh = 80, // T2
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M3_DioLow = 70, // T2i
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M3_DioLow = 70, // T2i
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M3_WrSetup = 30, // T3
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M3_WrSetup = 30, // T3
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M3_WrHold = 10, // T4
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M3_WrHold = 10, // T4
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M3_DoutSetup = 20, // T5
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M3_DoutSetup = 20, // T5
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M3_DoutHold = 5, // T6
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M3_DoutHold = 5, // T6
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M3_AddrHold = 10, // T9
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M3_AddrHold = 10, // T9
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|
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// ATA Mode 4 Timing
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// ATA Mode 4 Timing
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M4_DioCycle = 120, // T0
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M4_DioCycle = 120, // T0
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M4_AddrSetup = 25, // T1
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M4_AddrSetup = 25, // T1
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M4_DioHigh = 70, // T2
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M4_DioHigh = 70, // T2
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M4_DioLow = 25, // T2i
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M4_DioLow = 25, // T2i
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M4_WrSetup = 20, // T3
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M4_WrSetup = 20, // T3
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M4_WrHold = 10, // T4
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M4_WrHold = 10, // T4
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M4_DoutSetup = 20, // T5
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M4_DoutSetup = 20, // T5
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M4_DoutHold = 5, // T6
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M4_DoutHold = 5, // T6
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M4_AddrHold = 10; // T9
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M4_AddrHold = 10; // T9
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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// ATA Mode 0 Timing //
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// ATA Mode 0 Timing //
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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// Output Delay Path
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// Output Delay Path
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if(mode==0) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)
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if(mode==0) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)
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(0,0,
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(0,0,
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M0_DoutHold, (M0_DioHigh - M0_DoutSetup),
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M0_DoutHold, (M0_DioHigh - M0_DoutSetup),
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M0_DoutHold, (M0_DioHigh - M0_DoutSetup) );
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M0_DoutHold, (M0_DioHigh - M0_DoutSetup) );
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// Write Data Setup/Hold Check
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// Write Data Setup/Hold Check
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$setuphold(negedge ata_diow, ata_data, M0_WrSetup, M0_WrHold, , ,ata_rst_m0 );
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$setuphold(negedge ata_diow, ata_data, M0_WrSetup, M0_WrHold, , ,ata_rst_m0 );
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// DioX Active time Check
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// DioX Active time Check
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$width(posedge ata_dior &&& ata_rst_m0, M0_DioHigh );
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$width(posedge ata_dior &&& ata_rst_m0, M0_DioHigh );
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$width(posedge ata_diow &&& ata_rst_m0, M0_DioHigh );
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$width(posedge ata_diow &&& ata_rst_m0, M0_DioHigh );
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|
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// DioX Min Cycle Width Check
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// DioX Min Cycle Width Check
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$period(posedge ata_dior &&& ata_rst_m0, M0_DioCycle );
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$period(posedge ata_dior &&& ata_rst_m0, M0_DioCycle );
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$period(posedge ata_diow &&& ata_rst_m0, M0_DioCycle );
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$period(posedge ata_diow &&& ata_rst_m0, M0_DioCycle );
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// Address Setup Hold Checks
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// Address Setup Hold Checks
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$setup(ata_da, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_da, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_cs0, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_cs0, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_cs1, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_cs1, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_da, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_da, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_cs0, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_cs0, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_cs1, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
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$setup(ata_cs1, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
|
|
|
$hold(ata_da, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
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$hold(ata_da, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
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$hold(ata_cs0, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
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$hold(ata_cs0, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
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$hold(ata_cs1, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
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$hold(ata_cs1, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
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$hold(ata_da, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
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$hold(ata_da, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
|
$hold(ata_cs0, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
|
$hold(ata_cs0, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
|
$hold(ata_cs1, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
|
$hold(ata_cs1, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
|
|
|
|
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
// ATA Mode 1 Timing //
|
// ATA Mode 1 Timing //
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
|
|
// Output Delay Path
|
// Output Delay Path
|
if(mode==1) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)
|
if(mode==1) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)
|
(0,0,
|
(0,0,
|
M1_DoutHold, (M1_DioHigh - M1_DoutSetup),
|
M1_DoutHold, (M1_DioHigh - M1_DoutSetup),
|
M1_DoutHold, (M1_DioHigh - M1_DoutSetup) );
|
M1_DoutHold, (M1_DioHigh - M1_DoutSetup) );
|
|
|
// Write Data Setup/Hold Check
|
// Write Data Setup/Hold Check
|
$setuphold(negedge ata_diow, ata_data, M1_WrSetup, M1_WrHold, , ,ata_rst_m1 );
|
$setuphold(negedge ata_diow, ata_data, M1_WrSetup, M1_WrHold, , ,ata_rst_m1 );
|
|
|
// DioX Active time Check
|
// DioX Active time Check
|
$width(posedge ata_dior &&& ata_rst_m1, M1_DioHigh );
|
$width(posedge ata_dior &&& ata_rst_m1, M1_DioHigh );
|
$width(posedge ata_diow &&& ata_rst_m1, M1_DioHigh );
|
$width(posedge ata_diow &&& ata_rst_m1, M1_DioHigh );
|
|
|
// DioX Min Cycle Width Check
|
// DioX Min Cycle Width Check
|
$period(posedge ata_dior &&& ata_rst_m1, M1_DioCycle );
|
$period(posedge ata_dior &&& ata_rst_m1, M1_DioCycle );
|
$period(posedge ata_diow &&& ata_rst_m1, M1_DioCycle );
|
$period(posedge ata_diow &&& ata_rst_m1, M1_DioCycle );
|
|
|
// Address Setup Hold Checks
|
// Address Setup Hold Checks
|
$setup(ata_da, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_da, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_cs0, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_cs0, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_cs1, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_cs1, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_da, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_da, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_cs0, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_cs0, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_cs1, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
|
$setup(ata_cs1, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
|
|
|
$hold(ata_da, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_da, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_cs0, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_cs0, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_cs1, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_cs1, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_da, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_da, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_cs0, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_cs0, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_cs1, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
|
$hold(ata_cs1, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
|
|
|
|
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
// ATA Mode 2 Timing //
|
// ATA Mode 2 Timing //
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
|
|
// Output Delay Path
|
// Output Delay Path
|
if(mode==2) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)
|
if(mode==2) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)
|
(0,0,
|
(0,0,
|
M2_DoutHold, (M2_DioHigh - M2_DoutSetup),
|
M2_DoutHold, (M2_DioHigh - M2_DoutSetup),
|
M2_DoutHold, (M2_DioHigh - M2_DoutSetup) );
|
M2_DoutHold, (M2_DioHigh - M2_DoutSetup) );
|
|
|
// Write Data Setup/Hold Check
|
// Write Data Setup/Hold Check
|
$setuphold(negedge ata_diow, ata_data, M2_WrSetup, M2_WrHold, , ,ata_rst_m2 );
|
$setuphold(negedge ata_diow, ata_data, M2_WrSetup, M2_WrHold, , ,ata_rst_m2 );
|
|
|
// DioX Active time Check
|
// DioX Active time Check
|
$width(posedge ata_dior &&& ata_rst_m2, M2_DioHigh );
|
$width(posedge ata_dior &&& ata_rst_m2, M2_DioHigh );
|
$width(posedge ata_diow &&& ata_rst_m2, M2_DioHigh );
|
$width(posedge ata_diow &&& ata_rst_m2, M2_DioHigh );
|
|
|
// DioX Min Cycle Width Check
|
// DioX Min Cycle Width Check
|
$period(posedge ata_dior &&& ata_rst_m2, M2_DioCycle );
|
$period(posedge ata_dior &&& ata_rst_m2, M2_DioCycle );
|
$period(posedge ata_diow &&& ata_rst_m2, M2_DioCycle );
|
$period(posedge ata_diow &&& ata_rst_m2, M2_DioCycle );
|
|
|
// Address Setup Hold Checks
|
// Address Setup Hold Checks
|
$setup(ata_da, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_da, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_cs0, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_cs0, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_cs1, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_cs1, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_da, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_da, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_cs0, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_cs0, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_cs1, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
|
$setup(ata_cs1, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
|
|
|
$hold(ata_da, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_da, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_cs0, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_cs0, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_cs1, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_cs1, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_da, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_da, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_cs0, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_cs0, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_cs1, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
|
$hold(ata_cs1, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
|
|
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
// ATA Mode 3 Timing //
|
// ATA Mode 3 Timing //
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
|
|
// Output Delay Path
|
// Output Delay Path
|
if(mode==3) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)
|
if(mode==3) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)
|
(0,0,
|
(0,0,
|
M3_DoutHold, (M3_DioHigh - M3_DoutSetup),
|
M3_DoutHold, (M3_DioHigh - M3_DoutSetup),
|
M3_DoutHold, (M3_DioHigh - M3_DoutSetup) );
|
M3_DoutHold, (M3_DioHigh - M3_DoutSetup) );
|
|
|
// Write Data Setup/Hold Check
|
// Write Data Setup/Hold Check
|
$setuphold(negedge ata_diow, ata_data, M3_WrSetup, M3_WrHold, , ,ata_rst_m3 );
|
$setuphold(negedge ata_diow, ata_data, M3_WrSetup, M3_WrHold, , ,ata_rst_m3 );
|
|
|
// DioX Active time Check
|
// DioX Active time Check
|
$width(posedge ata_dior &&& ata_rst_m3, M3_DioHigh );
|
$width(posedge ata_dior &&& ata_rst_m3, M3_DioHigh );
|
$width(posedge ata_diow &&& ata_rst_m3, M3_DioHigh );
|
$width(posedge ata_diow &&& ata_rst_m3, M3_DioHigh );
|
|
|
$width(negedge ata_dior &&& ata_rst_m3, M3_DioLow );
|
$width(negedge ata_dior &&& ata_rst_m3, M3_DioLow );
|
$width(negedge ata_diow &&& ata_rst_m3, M3_DioLow );
|
$width(negedge ata_diow &&& ata_rst_m3, M3_DioLow );
|
|
|
// DioX Min Cycle Width Check
|
// DioX Min Cycle Width Check
|
$period(posedge ata_dior &&& ata_rst_m3, M3_DioCycle );
|
$period(posedge ata_dior &&& ata_rst_m3, M3_DioCycle );
|
$period(posedge ata_diow &&& ata_rst_m3, M3_DioCycle );
|
$period(posedge ata_diow &&& ata_rst_m3, M3_DioCycle );
|
|
|
// Address Setup Hold Checks
|
// Address Setup Hold Checks
|
$setup(ata_da, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_da, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_cs0, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_cs0, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_cs1, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_cs1, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_da, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_da, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_cs0, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_cs0, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_cs1, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
|
$setup(ata_cs1, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
|
|
|
$hold(ata_da, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_da, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_cs0, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_cs0, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_cs1, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_cs1, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_da, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_da, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_cs0, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_cs0, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_cs1, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
|
$hold(ata_cs1, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
|
|
|
|
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
// ATA Mode 4 Timing //
|
// ATA Mode 4 Timing //
|
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
|
|
// Output Delay Path
|
// Output Delay Path
|
if(mode==4) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)
|
if(mode==4) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)
|
(0,0,
|
(0,0,
|
M4_DoutHold, (M4_DioHigh - M4_DoutSetup),
|
M4_DoutHold, (M4_DioHigh - M4_DoutSetup),
|
M4_DoutHold, (M4_DioHigh - M4_DoutSetup) );
|
M4_DoutHold, (M4_DioHigh - M4_DoutSetup) );
|
|
|
// Write Data Setup/Hold Check
|
// Write Data Setup/Hold Check
|
$setuphold(negedge ata_diow, ata_data, M4_WrSetup, M4_WrHold, , ,ata_rst_m4 );
|
$setuphold(negedge ata_diow, ata_data, M4_WrSetup, M4_WrHold, , ,ata_rst_m4 );
|
|
|
// DioX Active time Check
|
// DioX Active time Check
|
$width(posedge ata_dior &&& ata_rst_m4, M4_DioHigh );
|
$width(posedge ata_dior &&& ata_rst_m4, M4_DioHigh );
|
$width(posedge ata_diow &&& ata_rst_m4, M4_DioHigh );
|
$width(posedge ata_diow &&& ata_rst_m4, M4_DioHigh );
|
|
|
$width(negedge ata_dior &&& ata_rst_m4, M4_DioLow );
|
$width(negedge ata_dior &&& ata_rst_m4, M4_DioLow );
|
$width(negedge ata_diow &&& ata_rst_m4, M4_DioLow );
|
$width(negedge ata_diow &&& ata_rst_m4, M4_DioLow );
|
|
|
// DioX Min Cycle Width Check
|
// DioX Min Cycle Width Check
|
$period(posedge ata_dior &&& ata_rst_m4, M4_DioCycle );
|
$period(posedge ata_dior &&& ata_rst_m4, M4_DioCycle );
|
$period(posedge ata_diow &&& ata_rst_m4, M4_DioCycle );
|
$period(posedge ata_diow &&& ata_rst_m4, M4_DioCycle );
|
|
|
// Address Setup Hold Checks
|
// Address Setup Hold Checks
|
$setup(ata_da, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_da, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_cs0, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_cs0, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_cs1, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_cs1, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_da, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_da, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_cs0, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_cs0, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_cs1, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
|
$setup(ata_cs1, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
|
|
|
$hold(ata_da, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_da, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_cs0, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_cs0, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_cs1, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_cs1, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_da, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_da, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_cs0, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_cs0, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_cs1, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
|
$hold(ata_cs1, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
|
|
|
|
|
|
|
endspecify
|
endspecify
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
