/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
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//// Top Level Test Bench ////
|
//// Top Level Test Bench ////
|
//// ////
|
//// ////
|
//// ////
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//// ////
|
//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
|
//// ////
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//// ////
|
//// ////
|
//// ////
|
//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////
|
//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
|
//// Copyright (C) 2001 Rudolf Usselmann ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
|
//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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|
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// CVS Log
|
// CVS Log
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//
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//
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// $Id: test_bench_top.v,v 1.1 2001-08-16 10:01:05 rudi Exp $
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// $Id: test_bench_top.v,v 1.2 2002-02-16 10:41:16 rherveille Exp $
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//
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//
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// $Date: 2001-08-16 10:01:05 $
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// $Date: 2002-02-16 10:41:16 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
|
// Change History:
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// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/16 10:01:05 rudi
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//
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// - Added Test Bench
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// - Added Synthesis scripts for Design Compiler
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// - Fixed minor bug in atahost_top
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//
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//
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//
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//
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//
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//
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//
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//
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//
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|
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`timescale 1ns / 10ps
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`timescale 1ns / 10ps
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module test;
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module test;
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reg clk;
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reg clk;
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reg rst;
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reg rst;
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|
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wire int;
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wire int;
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wire [31:0] wb_addr_i;
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wire [31:0] wb_addr_i;
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wire [31:0] wb_data_i;
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wire [31:0] wb_data_i;
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wire [31:0] wb_data_o;
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wire [31:0] wb_data_o;
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wire [3:0] wb_sel_i;
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wire [3:0] wb_sel_i;
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wire wb_we_i;
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wire wb_we_i;
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wire wb_stb_i;
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wire wb_stb_i;
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wire wb_cyc_i;
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wire wb_cyc_i;
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wire wb_ack_o;
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wire wb_ack_o;
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wire wb_err_o;
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wire wb_err_o;
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wire ata_rst_;
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wire ata_rst_;
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wire [15:0] ata_dout;
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wire [15:0] ata_dout;
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wire [15:0] ata_din;
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wire [15:0] ata_din;
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wire [15:0] ata_data;
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wire [15:0] ata_data;
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wire ata_doe;
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wire ata_doe;
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wire [2:0] ata_da;
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wire [2:0] ata_da;
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wire ata_cs0, ata_cs1;
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wire ata_cs0, ata_cs1;
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wire ata_dior, ata_diow;
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wire ata_dior, ata_diow;
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wire ata_iordy;
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wire ata_iordy;
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wire ata_intrq;
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wire ata_intrq;
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reg ata_intrq_r;
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reg ata_intrq_r;
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// Test Bench Variables
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// Test Bench Variables
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integer wd_cnt;
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integer wd_cnt;
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integer error_cnt;
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integer error_cnt;
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integer verbose;
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integer verbose;
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// Misc Variables
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// Misc Variables
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//
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//
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// Defines
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// Defines
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//
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//
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`define CTRL 32'h0000_0000
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`define CTRL 32'h0000_0000
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`define STAT 32'h0000_0004
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`define STAT 32'h0000_0004
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`define PCTR 32'h0000_0008
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`define PCTR 32'h0000_0008
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`define ATA_DEV 32'h0000_0040
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`define ATA_DEV 32'h0000_0040
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|
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//
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//
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// Simulation Initialization and Start up Section
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// Simulation Initialization and Start up Section
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//
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//
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initial
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initial
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begin
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begin
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$display("\n\n");
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$display("\n\n");
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$display("******************************************************");
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$display("******************************************************");
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$display("* WISHBONE ATA 1 Controller Simulation started ... *");
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$display("* WISHBONE ATA 1 Controller Simulation started ... *");
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$display("******************************************************");
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$display("******************************************************");
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$display("\n");
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$display("\n");
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`ifdef WAVES
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`ifdef WAVES
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$shm_open("waves");
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$shm_open("waves");
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$shm_probe("AS",test,"AS");
|
$shm_probe("AS",test,"AS");
|
$display("INFO: Signal dump enabled ...\n\n");
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$display("INFO: Signal dump enabled ...\n\n");
|
`endif
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`endif
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wd_cnt = 0;
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wd_cnt = 0;
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error_cnt = 0;
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error_cnt = 0;
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clk = 0;
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clk = 0;
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rst = 0;
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rst = 0;
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verbose = 1;
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verbose = 1;
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ata_intrq_r=0;
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ata_intrq_r=0;
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|
|
repeat(10) @(posedge clk);
|
repeat(10) @(posedge clk);
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rst = 1;
|
rst = 1;
|
repeat(10) @(posedge clk);
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repeat(10) @(posedge clk);
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|
|
// HERE IS WHERE THE TEST CASES GO ...
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// HERE IS WHERE THE TEST CASES GO ...
|
|
|
if(1) // Full Regression Run
|
if(1) // Full Regression Run
|
begin
|
begin
|
io_test1;
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io_test1;
|
io_test2;
|
io_test2;
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int_test;
|
int_test;
|
rst_test;
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rst_test;
|
|
|
end
|
end
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else
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else
|
begin
|
begin
|
|
|
//
|
//
|
// TEST DEVELOPMENT AREA
|
// TEST DEVELOPMENT AREA
|
//
|
//
|
$display("\n\n");
|
$display("\n\n");
|
$display("*****************************************************");
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$display("*****************************************************");
|
$display("*** DEVELOPMENT Test ***");
|
$display("*** DEVELOPMENT Test ***");
|
$display("*****************************************************\n");
|
$display("*****************************************************\n");
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|
|
|
|
|
|
|
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show_errors;
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show_errors;
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$display("*****************************************************");
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$display("*****************************************************");
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$display("*** Test DONE ... ***");
|
$display("*** Test DONE ... ***");
|
$display("*****************************************************\n\n");
|
$display("*****************************************************\n\n");
|
|
|
end
|
end
|
repeat(100) @(posedge clk);
|
repeat(100) @(posedge clk);
|
$finish;
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$finish;
|
end
|
end
|
|
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//
|
//
|
// System Clock (100Mhz)
|
// System Clock (100Mhz)
|
//
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//
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|
|
always #5 clk = ~clk;
|
always #5 clk = ~clk;
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|
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Watchdog Counter
|
// Watchdog Counter
|
// Terminate simulation if nothing happens ...
|
// Terminate simulation if nothing happens ...
|
//
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//
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|
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always @(wb_cyc_i or wb_ack_o)
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always @(wb_cyc_i or wb_ack_o)
|
wd_cnt <= #5 0;
|
wd_cnt <= #5 0;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
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wd_cnt <= #1 wd_cnt + 1;
|
wd_cnt <= #1 wd_cnt + 1;
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|
|
always @(wd_cnt)
|
always @(wd_cnt)
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if(wd_cnt>5000)
|
if(wd_cnt>5000)
|
begin
|
begin
|
$display("\n\n*************************************\n");
|
$display("\n\n*************************************\n");
|
$display("ERROR: Watch Dog Counter Expired\n");
|
$display("ERROR: Watch Dog Counter Expired\n");
|
$display("*************************************\n\n\n");
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$display("*************************************\n\n\n");
|
$finish;
|
$finish;
|
end
|
end
|
|
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//
|
//
|
// DUT & Models
|
// DUT & Models
|
//
|
//
|
|
|
// Create an external Tri-State Bus to the ATA Device
|
// Create an external Tri-State Bus to the ATA Device
|
assign ata_din = ata_data;
|
assign ata_din = ata_data;
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assign ata_data = ata_doe ? ata_dout : 16'hzzzz;
|
assign ata_data = ata_doe ? ata_dout : 16'hzzzz;
|
|
|
// DUT: ATA Host
|
// DUT: ATA Host
|
atahost_top u0( //-- WISHBONE SYSCON signals
|
atahost_top u0( //-- WISHBONE SYSCON signals
|
.wb_clk_i( clk ),
|
.wb_clk_i( clk ),
|
.rst_nreset_i( rst ),
|
.arst_i( rst ),
|
.wb_rst_i( ~rst ),
|
.wb_rst_i( ~rst ),
|
|
|
//-- WISHBONE SLAVE signals
|
//-- WISHBONE SLAVE signals
|
.wb_cyc_i( wb_cyc_i ),
|
.wb_cyc_i( wb_cyc_i ),
|
.wb_stb_i( wb_stb_i ),
|
.wb_stb_i( wb_stb_i ),
|
.wb_ack_o( wb_ack_o ),
|
.wb_ack_o( wb_ack_o ),
|
.wb_err_o( wb_err_o ),
|
.wb_err_o( wb_err_o ),
|
.wb_adr_i( wb_addr_i[6:2] ),
|
.wb_adr_i( wb_addr_i[6:2] ),
|
.wb_dat_i( wb_data_i ),
|
.wb_dat_i( wb_data_i ),
|
.wb_dat_o( wb_data_o ),
|
.wb_dat_o( wb_data_o ),
|
.wb_sel_i( wb_sel_i ),
|
.wb_sel_i( wb_sel_i ),
|
.wb_we_i( wb_we_i ),
|
.wb_we_i( wb_we_i ),
|
.wb_inta_o( int ),
|
.wb_inta_o( int ),
|
|
|
//-- ATA signals
|
//-- ATA signals
|
.ata_resetn_pad_o( ata_rst_ ),
|
.resetn_pad_o( ata_rst_ ),
|
.ata_dd_pad_i( ata_din ),
|
.dd_pad_i( ata_din ),
|
.ata_dd_pad_o( ata_dout ),
|
.dd_pad_o( ata_dout ),
|
.ata_dd_pad_oe( ata_doe ),
|
.dd_padoe_o( ata_doe ),
|
.ata_da_pad_o( ata_da ),
|
.da_pad_o( ata_da ),
|
.ata_cs0n_pad_o( ata_cs0 ),
|
.cs0n_pad_o( ata_cs0 ),
|
.ata_cs1n_pad_o( ata_cs1 ),
|
.cs1n_pad_o( ata_cs1 ),
|
.ata_diorn_pad_o( ata_dior_ ),
|
.diorn_pad_o( ata_dior_ ),
|
.ata_diown_pad_o( ata_diow_ ),
|
.diown_pad_o( ata_diow_ ),
|
.ata_iordy_pad_i( ata_iordy ),
|
.iordy_pad_i( ata_iordy ),
|
.ata_intrq_pad_i( ata_intrq_r )
|
.intrq_pad_i( ata_intrq_r )
|
);
|
);
|
|
|
// ATA Device Model
|
// ATA Device Model
|
ata_device a0( .ata_rst_( ata_rst_ ),
|
ata_device a0( .ata_rst_( ata_rst_ ),
|
.ata_data( ata_data ),
|
.ata_data( ata_data ),
|
.ata_da( ata_da ),
|
.ata_da( ata_da ),
|
.ata_cs0( ata_cs0 ),
|
.ata_cs0( ata_cs0 ),
|
.ata_cs1( ata_cs1 ),
|
.ata_cs1( ata_cs1 ),
|
.ata_dior_( ata_dior_ ),
|
.ata_dior_( ata_dior_ ),
|
.ata_diow_( ata_diow_ ),
|
.ata_diow_( ata_diow_ ),
|
.ata_iordy( ata_iordy ),
|
.ata_iordy( ata_iordy ),
|
.ata_intrq( ata_intrq ) );
|
.ata_intrq( ata_intrq ) );
|
|
|
// WISHBONE Master Model
|
// WISHBONE Master Model
|
wb_mast m0( .clk( clk ),
|
wb_mast m0( .clk( clk ),
|
.rst( rst ),
|
.rst( rst ),
|
.adr( wb_addr_i ),
|
.adr( wb_addr_i ),
|
.din( wb_data_o ),
|
.din( wb_data_o ),
|
.dout( wb_data_i ),
|
.dout( wb_data_i ),
|
.cyc( wb_cyc_i ),
|
.cyc( wb_cyc_i ),
|
.stb( wb_stb_i ),
|
.stb( wb_stb_i ),
|
.sel( wb_sel_i ),
|
.sel( wb_sel_i ),
|
.we( wb_we_i ),
|
.we( wb_we_i ),
|
.ack( wb_ack_o ),
|
.ack( wb_ack_o ),
|
.err( wb_err_o ),
|
.err( wb_err_o ),
|
.rty( 1'b0 ) );
|
.rty( 1'b0 ) );
|
|
|
// External Tests
|
// External Tests
|
`include "tests.v"
|
`include "tests.v"
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
