/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE Master Model ////
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//// WISHBONE Master Model ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
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//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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|
|
// CVS Log
|
// CVS Log
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//
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//
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// $Id: wb_mast_model.v,v 1.1 2001-08-16 10:01:05 rudi Exp $
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// $Id: wb_mast_model.v,v 1.1 2001-08-16 10:01:05 rudi Exp $
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//
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//
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// $Date: 2001-08-16 10:01:05 $
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// $Date: 2001-08-16 10:01:05 $
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// $Revision: 1.1 $
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// $Revision: 1.1 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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|
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/*
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/*
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task mem_fill;
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task mem_fill;
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- Fills local burst read (rd_buf[]) and write(wr_buf[]) buffers with random values.
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- Fills local burst read (rd_buf[]) and write(wr_buf[]) buffers with random values.
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task wb_wr1( 32 bit address, 4 bit byte select, 32 bit write data);
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task wb_wr1( 32 bit address, 4 bit byte select, 32 bit write data);
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|
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- Performs a single WISHBONE write
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- Performs a single WISHBONE write
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|
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task wb_wr4( 32 bit address, 4 bit byte select, integer delay,
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task wb_wr4( 32 bit address, 4 bit byte select, integer delay,
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32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);
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32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);
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|
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- Performs 4 consecutive WISHBONE writes
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- Performs 4 consecutive WISHBONE writes
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- Strobe is deasserted between writes for 'delay' number of cycles
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- Strobe is deasserted between writes for 'delay' number of cycles
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(This simulates wait state insertion ...)
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(This simulates wait state insertion ...)
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task wb_wr_mult( 32 bit address, 4 bit byte select, integer delay,
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task wb_wr_mult( 32 bit address, 4 bit byte select, integer delay,
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integer count);
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integer count);
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|
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- Simular to wb_wr4, except it pwrforms "count" number of write cycles.
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- Simular to wb_wr4, except it pwrforms "count" number of write cycles.
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The data is taken from the internal wr_bub[] memory.
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The data is taken from the internal wr_bub[] memory.
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- Strobe is deasserted between writes for 'delay' number of cycles
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- Strobe is deasserted between writes for 'delay' number of cycles
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(This simulates wait state insertion ...)
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(This simulates wait state insertion ...)
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task wb_rmw( 32 bit address, 4 bit byte select, integer delay,
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task wb_rmw( 32 bit address, 4 bit byte select, integer delay,
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integer rcount, integer wcount);
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integer rcount, integer wcount);
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|
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- This task performs "rcount" read cycles, followed by wcount write cycles.
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- This task performs "rcount" read cycles, followed by wcount write cycles.
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- read data is placed in to the internal rd_buf[] memory, write data is
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- read data is placed in to the internal rd_buf[] memory, write data is
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taken from the internal wr_buf[] memory.
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taken from the internal wr_buf[] memory.
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- Strobe is deasserted between writes for 'delay' number of cycles
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- Strobe is deasserted between writes for 'delay' number of cycles
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(This simulates wait state insertion ...)
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(This simulates wait state insertion ...)
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task wb_rd1( 32 bit address, 4 bit byte select, 32 bit read data);
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task wb_rd1( 32 bit address, 4 bit byte select, 32 bit read data);
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|
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- Performs a single WISHBONE write
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- Performs a single WISHBONE write
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|
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task wb_rd4( 32 bit address, 4 bit byte select, integer delay,
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task wb_rd4( 32 bit address, 4 bit byte select, integer delay,
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32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);
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32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);
|
|
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- Performs 4 consecutive WISHBONE reads
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- Performs 4 consecutive WISHBONE reads
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- Strobe is deasserted between reads for 'delay' number of cycles
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- Strobe is deasserted between reads for 'delay' number of cycles
|
(This simulates wait state insertion ...)
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(This simulates wait state insertion ...)
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|
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task wb_rd_mult( 32 bit address, 4 bit byte select, integer delay,
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task wb_rd_mult( 32 bit address, 4 bit byte select, integer delay,
|
integer count);
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integer count);
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|
|
- Simular to wb_rd4, except it pwrforms "count" number of read cycles.
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- Simular to wb_rd4, except it pwrforms "count" number of read cycles.
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The data is read in to the internal rd_buf[] memory.
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The data is read in to the internal rd_buf[] memory.
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- Strobe is deasserted between reads for 'delay' number of cycles
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- Strobe is deasserted between reads for 'delay' number of cycles
|
(This simulates wait state insertion ...)
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(This simulates wait state insertion ...)
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|
|
|
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*/
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*/
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`include "wb_model_defines.v"
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`include "wb_model_defines.v"
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|
|
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
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module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
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|
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input clk, rst;
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input clk, rst;
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output [31:0] adr;
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output [31:0] adr;
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input [31:0] din;
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input [31:0] din;
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output [31:0] dout;
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output [31:0] dout;
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output cyc, stb;
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output cyc, stb;
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output [3:0] sel;
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output [3:0] sel;
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output we;
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output we;
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input ack, err, rty;
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input ack, err, rty;
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|
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires
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// Local Wires
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//
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//
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parameter mem_size = 4096;
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parameter mem_size = 4096;
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|
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reg [31:0] adr;
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reg [31:0] adr;
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reg [31:0] dout;
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reg [31:0] dout;
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reg cyc, stb;
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reg cyc, stb;
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reg [3:0] sel;
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reg [3:0] sel;
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reg we;
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reg we;
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reg [31:0] rd_mem[mem_size:0];
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reg [31:0] rd_mem[mem_size:0];
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reg [31:0] wr_mem[mem_size:0];
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reg [31:0] wr_mem[mem_size:0];
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integer rd_cnt;
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integer rd_cnt;
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integer wr_cnt;
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integer wr_cnt;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Memory Logic
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// Memory Logic
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//
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//
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initial
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initial
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begin
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begin
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adr = 32'hxxxx_xxxx;
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adr = 32'hxxxx_xxxx;
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dout = 32'hxxxx_xxxx;
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dout = 32'hxxxx_xxxx;
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cyc = 0;
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cyc = 0;
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stb = 0;
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stb = 0;
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sel = 4'hx;
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sel = 4'hx;
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we = 1'hx;
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we = 1'hx;
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rd_cnt = 0;
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rd_cnt = 0;
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wr_cnt = 0;
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wr_cnt = 0;
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#1;
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#1;
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$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
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$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
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end
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end
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task mem_fill;
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task mem_fill;
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|
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integer n;
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integer n;
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begin
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begin
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rd_cnt = 0;
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rd_cnt = 0;
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wr_cnt = 0;
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wr_cnt = 0;
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for(n=0;n<mem_size;n=n+1)
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for(n=0;n<mem_size;n=n+1)
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begin
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begin
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rd_mem[n] = $random;
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rd_mem[n] = $random;
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wr_mem[n] = $random;
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wr_mem[n] = $random;
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end
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end
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end
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end
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endtask
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endtask
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|
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Write 1 Word Task
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// Write 1 Word Task
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//
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//
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|
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task wb_wr1;
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task wb_wr1;
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input [31:0] a;
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input [31:0] a;
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input [3:0] s;
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input [3:0] s;
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input [31:0] d;
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input [31:0] d;
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|
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begin
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begin
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|
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@(posedge clk);
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@(posedge clk);
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#1;
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#1;
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adr = a;
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adr = a;
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dout = d;
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dout = d;
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cyc = 1;
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cyc = 1;
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stb = 1;
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stb = 1;
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we=1;
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we=1;
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sel = s;
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sel = s;
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|
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@(posedge clk);
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@(posedge clk);
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while(~ack & ~err) @(posedge clk);
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while(~ack & ~err) @(posedge clk);
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#1;
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#1;
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cyc=0;
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cyc=0;
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stb=0;
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stb=0;
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adr = 32'hxxxx_xxxx;
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adr = 32'hxxxx_xxxx;
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dout = 32'hxxxx_xxxx;
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dout = 32'hxxxx_xxxx;
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we = 1'hx;
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we = 1'hx;
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sel = 4'hx;
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sel = 4'hx;
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|
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end
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end
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endtask
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endtask
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Write 4 Words Task
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// Write 4 Words Task
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//
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//
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|
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task wb_wr4;
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task wb_wr4;
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input [31:0] a;
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input [31:0] a;
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input [3:0] s;
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input [3:0] s;
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input delay;
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input delay;
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input [31:0] d1;
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input [31:0] d1;
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input [31:0] d2;
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input [31:0] d2;
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input [31:0] d3;
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input [31:0] d3;
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input [31:0] d4;
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input [31:0] d4;
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|
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integer delay;
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integer delay;
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begin
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begin
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|
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@(posedge clk);
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@(posedge clk);
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#1;
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#1;
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cyc = 1;
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cyc = 1;
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sel = s;
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sel = s;
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|
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repeat(delay)
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repeat(delay)
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begin
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begin
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@(posedge clk);
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@(posedge clk);
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#1;
|
#1;
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end
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end
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adr = a;
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adr = a;
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dout = d1;
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dout = d1;
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stb = 1;
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stb = 1;
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we=1;
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we=1;
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while(~ack & ~err) @(posedge clk);
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while(~ack & ~err) @(posedge clk);
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#2;
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#2;
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stb=0;
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stb=0;
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we=1'bx;
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we=1'bx;
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dout = 32'hxxxx_xxxx;
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dout = 32'hxxxx_xxxx;
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adr = 32'hxxxx_xxxx;
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adr = 32'hxxxx_xxxx;
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|
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repeat(delay)
|
repeat(delay)
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begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
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#1;
|
#1;
|
end
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end
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stb=1;
|
stb=1;
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adr = a+4;
|
adr = a+4;
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dout = d2;
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dout = d2;
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we=1;
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we=1;
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@(posedge clk);
|
@(posedge clk);
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while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we=1'bx;
|
we=1'bx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
|
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
stb=1;
|
stb=1;
|
adr = a+8;
|
adr = a+8;
|
dout = d3;
|
dout = d3;
|
we=1;
|
we=1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we=1'bx;
|
we=1'bx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
|
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
stb=1;
|
stb=1;
|
adr = a+12;
|
adr = a+12;
|
dout = d4;
|
dout = d4;
|
we=1;
|
we=1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#1;
|
#1;
|
stb=0;
|
stb=0;
|
cyc=0;
|
cyc=0;
|
|
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task wb_wr_mult;
|
task wb_wr_mult;
|
input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
input delay;
|
input delay;
|
input count;
|
input count;
|
|
|
integer delay;
|
integer delay;
|
integer count;
|
integer count;
|
integer n;
|
integer n;
|
|
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
cyc = 1;
|
cyc = 1;
|
|
|
for(n=0;n<count;n=n+1)
|
for(n=0;n<count;n=n+1)
|
begin
|
begin
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
adr = a + (n*4);
|
adr = a + (n*4);
|
dout = wr_mem[n + wr_cnt];
|
dout = wr_mem[n + wr_cnt];
|
stb = 1;
|
stb = 1;
|
we=1;
|
we=1;
|
sel = s;
|
sel = s;
|
if(n!=0) @(posedge clk);
|
if(n!=0) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we=1'bx;
|
we=1'bx;
|
sel = 4'hx;
|
sel = 4'hx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
end
|
end
|
|
|
cyc=0;
|
cyc=0;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
|
|
wr_cnt = wr_cnt + count;
|
wr_cnt = wr_cnt + count;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task wb_rmw;
|
task wb_rmw;
|
input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
input delay;
|
input delay;
|
input rcount;
|
input rcount;
|
input wcount;
|
input wcount;
|
|
|
integer delay;
|
integer delay;
|
integer rcount;
|
integer rcount;
|
integer wcount;
|
integer wcount;
|
integer n;
|
integer n;
|
|
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
cyc = 1;
|
cyc = 1;
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
repeat(delay) @(posedge clk);
|
repeat(delay) @(posedge clk);
|
|
|
for(n=0;n<rcount-1;n=n+1)
|
for(n=0;n<rcount-1;n=n+1)
|
begin
|
begin
|
adr = a + (n*4);
|
adr = a + (n*4);
|
stb = 1;
|
stb = 1;
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
rd_mem[n + rd_cnt] = din;
|
rd_mem[n + rd_cnt] = din;
|
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
|
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
end
|
end
|
|
|
adr = a+(n*4);
|
adr = a+(n*4);
|
stb = 1;
|
stb = 1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
rd_mem[n + rd_cnt] = din;
|
rd_mem[n + rd_cnt] = din;
|
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
|
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
|
#1;
|
#1;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
|
|
rd_cnt = rd_cnt + rcount;
|
rd_cnt = rd_cnt + rcount;
|
|
|
for(n=0;n<wcount;n=n+1)
|
for(n=0;n<wcount;n=n+1)
|
begin
|
begin
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
adr = a + (n*4);
|
adr = a + (n*4);
|
dout = wr_mem[n + wr_cnt];
|
dout = wr_mem[n + wr_cnt];
|
stb = 1;
|
stb = 1;
|
we=1;
|
we=1;
|
sel = s;
|
sel = s;
|
// if(n!=0)
|
// if(n!=0)
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we=1'bx;
|
we=1'bx;
|
sel = 4'hx;
|
sel = 4'hx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
end
|
end
|
|
|
cyc=0;
|
cyc=0;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
|
|
wr_cnt = wr_cnt + wcount;
|
wr_cnt = wr_cnt + wcount;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Read 1 Word Task
|
// Read 1 Word Task
|
//
|
//
|
|
|
task wb_rd1;
|
task wb_rd1;
|
input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
output [31:0] d;
|
output [31:0] d;
|
|
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
adr = a;
|
adr = a;
|
cyc = 1;
|
cyc = 1;
|
stb = 1;
|
stb = 1;
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
|
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
d = din;
|
d = din;
|
#1;
|
#1;
|
cyc=0;
|
cyc=0;
|
stb=0;
|
stb=0;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
dout = 32'hxxxx_xxxx;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Read 4 Words Task
|
// Read 4 Words Task
|
//
|
//
|
|
|
|
|
task wb_rd4;
|
task wb_rd4;
|
input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
input delay;
|
input delay;
|
output [31:0] d1;
|
output [31:0] d1;
|
output [31:0] d2;
|
output [31:0] d2;
|
output [31:0] d3;
|
output [31:0] d3;
|
output [31:0] d4;
|
output [31:0] d4;
|
|
|
integer delay;
|
integer delay;
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
cyc = 1;
|
cyc = 1;
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
repeat(delay) @(posedge clk);
|
repeat(delay) @(posedge clk);
|
|
|
adr = a;
|
adr = a;
|
stb = 1;
|
stb = 1;
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
d1 = din;
|
d1 = din;
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
|
|
adr = a+4;
|
adr = a+4;
|
stb = 1;
|
stb = 1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
d2 = din;
|
d2 = din;
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
|
|
|
|
adr = a+8;
|
adr = a+8;
|
stb = 1;
|
stb = 1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
d3 = din;
|
d3 = din;
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
|
|
adr = a+12;
|
adr = a+12;
|
stb = 1;
|
stb = 1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
d4 = din;
|
d4 = din;
|
#1;
|
#1;
|
stb=0;
|
stb=0;
|
cyc=0;
|
cyc=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task wb_rd_mult;
|
task wb_rd_mult;
|
input [31:0] a;
|
input [31:0] a;
|
input [3:0] s;
|
input [3:0] s;
|
input delay;
|
input delay;
|
input count;
|
input count;
|
|
|
integer delay;
|
integer delay;
|
integer count;
|
integer count;
|
integer n;
|
integer n;
|
|
|
begin
|
begin
|
|
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
cyc = 1;
|
cyc = 1;
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
repeat(delay) @(posedge clk);
|
repeat(delay) @(posedge clk);
|
|
|
for(n=0;n<count-1;n=n+1)
|
for(n=0;n<count-1;n=n+1)
|
begin
|
begin
|
adr = a + (n*4);
|
adr = a + (n*4);
|
stb = 1;
|
stb = 1;
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
rd_mem[n + rd_cnt] = din;
|
rd_mem[n + rd_cnt] = din;
|
#2;
|
#2;
|
stb=0;
|
stb=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
repeat(delay)
|
repeat(delay)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
#1;
|
#1;
|
end
|
end
|
we = 0;
|
we = 0;
|
sel = s;
|
sel = s;
|
end
|
end
|
|
|
adr = a+(n*4);
|
adr = a+(n*4);
|
stb = 1;
|
stb = 1;
|
@(posedge clk);
|
@(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
while(~ack & ~err) @(posedge clk);
|
rd_mem[n + rd_cnt] = din;
|
rd_mem[n + rd_cnt] = din;
|
#1;
|
#1;
|
stb=0;
|
stb=0;
|
cyc=0;
|
cyc=0;
|
we = 1'hx;
|
we = 1'hx;
|
sel = 4'hx;
|
sel = 4'hx;
|
adr = 32'hxxxx_xxxx;
|
adr = 32'hxxxx_xxxx;
|
|
|
rd_cnt = rd_cnt + count;
|
rd_cnt = rd_cnt + count;
|
end
|
end
|
endtask
|
endtask
|
|
|
endmodule
|
endmodule
|
|
|