/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Generic Up/Down counter ////
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//// Generic Up/Down counter ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ud_cnt.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $
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// $Id: ud_cnt.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $
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//
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//
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// $Date: 2002-02-16 10:42:17 $
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// $Date: 2002-02-16 10:42:17 $
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// $Revision: 1.2 $
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// $Revision: 1.2 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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/////////////////////////////
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/////////////////////////////
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// general purpose counter //
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// general purpose counter //
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/////////////////////////////
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/////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, rci, rco);
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module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, rci, rco);
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// parameter declaration
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// parameter declaration
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parameter SIZE = 8;
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parameter SIZE = 8;
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parameter RESD = {SIZE{1'b0}}; // data after reset
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parameter RESD = {SIZE{1'b0}}; // data after reset
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// inputs & outputs
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// inputs & outputs
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input clk; // master clock
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input clk; // master clock
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input nReset; // asynchronous active low reset
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input nReset; // asynchronous active low reset
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input rst; // synchronous active high reset
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input rst; // synchronous active high reset
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input cnt_en; // count enable
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input cnt_en; // count enable
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input ud; // up/not down
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input ud; // up/not down
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input nld; // synchronous active low load
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input nld; // synchronous active low load
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input [SIZE-1:0] d; // load counter value
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input [SIZE-1:0] d; // load counter value
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output [SIZE-1:0] q; // current counter value
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output [SIZE-1:0] q; // current counter value
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input rci; // carry input
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input rci; // carry input
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output rco; // carry output
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output rco; // carry output
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// variable declarations
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// variable declarations
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reg [SIZE-1:0] Qi; // intermediate value
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reg [SIZE-1:0] Qi; // intermediate value
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wire [SIZE:0] val; // carry+result
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wire [SIZE:0] val; // carry+result
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//
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//
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// Module body
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// Module body
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//
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//
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assign val = ud ? ( {1'b0, Qi} + rci) : ( {1'b0, Qi} - rci);
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assign val = ud ? ( {1'b0, Qi} + rci) : ( {1'b0, Qi} - rci);
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always@(posedge clk or negedge nReset)
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always@(posedge clk or negedge nReset)
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begin
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begin
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if (~nReset)
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if (~nReset)
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Qi <= #1 RESD;
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Qi <= #1 RESD;
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else if (rst)
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else if (rst)
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Qi <= #1 RESD;
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Qi <= #1 RESD;
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else if (~nld)
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else if (~nld)
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Qi <= #1 d;
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Qi <= #1 d;
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else if (cnt_en)
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else if (cnt_en)
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Qi <= #1 val[SIZE-1:0];
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Qi <= #1 val[SIZE-1:0];
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end
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end
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// assign outputs
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// assign outputs
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assign q = Qi;
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assign q = Qi;
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assign rco = val[SIZE];
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assign rco = val[SIZE];
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endmodule
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endmodule
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