/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OpenCores ATA/ATAPI-5 Host Controller ////
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//// OpenCores ATA/ATAPI-5 Host Controller ////
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//// ATA/ATAPI-5 PIO Controller (OCIDEC-2) ////
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//// ATA/ATAPI-5 PIO Controller (OCIDEC-2) ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Log
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// CVS Log
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//
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//
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// $Id: atahost_controller.v,v 1.2 2002-05-19 06:05:28 rherveille Exp $
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// $Id: atahost_controller.v,v 1.2 2002-05-19 06:05:28 rherveille Exp $
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//
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//
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// $Date: 2002-05-19 06:05:28 $
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// $Date: 2002-05-19 06:05:28 $
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// $Revision: 1.2 $
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// $Revision: 1.2 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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// OCIDEC2 supports:
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// OCIDEC2 supports:
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// -Common Compatible timing access to all connected devices
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// -Common Compatible timing access to all connected devices
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// -Separate timing accesses to data port
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// -Separate timing accesses to data port
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// -No DMA support
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// -No DMA support
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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module atahost_controller (
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module atahost_controller (
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clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1,
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clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1,
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cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen,
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cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen,
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dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen,
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dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen,
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dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen,
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dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen,
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PIOreq, PIOack, PIOa, PIOd, PIOq, PIOwe,
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PIOreq, PIOack, PIOa, PIOd, PIOq, PIOwe,
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RESETn, DDi, DDo, DDoe, DA, CS0n, CS1n, DIORn, DIOWn, IORDY, INTRQ
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RESETn, DDi, DDo, DDoe, DA, CS0n, CS1n, DIORn, DIOWn, IORDY, INTRQ
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);
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);
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//
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//
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// parameters
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// parameters
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//
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//
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parameter TWIDTH = 8;
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parameter TWIDTH = 8;
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parameter PIO_mode0_T1 = 6; // 70ns
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parameter PIO_mode0_T1 = 6; // 70ns
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parameter PIO_mode0_T2 = 28; // 290ns
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parameter PIO_mode0_T2 = 28; // 290ns
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parameter PIO_mode0_T4 = 2; // 30ns
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parameter PIO_mode0_T4 = 2; // 30ns
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parameter PIO_mode0_Teoc = 23; // 240ns
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parameter PIO_mode0_Teoc = 23; // 240ns
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//
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//
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// inputs & outputs
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// inputs & outputs
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//
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//
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input clk; // master clock
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input clk; // master clock
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input nReset; // asynchronous active low reset
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input nReset; // asynchronous active low reset
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input rst; // synchronous active high reset
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input rst; // synchronous active high reset
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output irq; // interrupt request signal
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output irq; // interrupt request signal
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reg irq;
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reg irq;
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// control / registers
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// control / registers
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input IDEctrl_rst;
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input IDEctrl_rst;
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input IDEctrl_IDEen;
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input IDEctrl_IDEen;
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input IDEctrl_FATR0;
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input IDEctrl_FATR0;
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input IDEctrl_FATR1;
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input IDEctrl_FATR1;
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input [7:0] cmdport_T1,
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input [7:0] cmdport_T1,
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cmdport_T2,
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cmdport_T2,
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cmdport_T4,
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cmdport_T4,
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cmdport_Teoc;
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cmdport_Teoc;
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input cmdport_IORDYen; // PIO command port / non-fast timing
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input cmdport_IORDYen; // PIO command port / non-fast timing
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input [7:0] dport0_T1,
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input [7:0] dport0_T1,
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dport0_T2,
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dport0_T2,
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dport0_T4,
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dport0_T4,
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dport0_Teoc;
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dport0_Teoc;
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input dport0_IORDYen; // PIO mode data-port / fast timing device 0
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input dport0_IORDYen; // PIO mode data-port / fast timing device 0
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input [7:0] dport1_T1,
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input [7:0] dport1_T1,
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dport1_T2,
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dport1_T2,
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dport1_T4,
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dport1_T4,
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dport1_Teoc;
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dport1_Teoc;
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input dport1_IORDYen; // PIO mode data-port / fast timing device 1
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input dport1_IORDYen; // PIO mode data-port / fast timing device 1
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input PIOreq; // PIO transfer request
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input PIOreq; // PIO transfer request
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output PIOack; // PIO transfer ended
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output PIOack; // PIO transfer ended
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input [ 3:0] PIOa; // PIO address
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input [ 3:0] PIOa; // PIO address
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input [15:0] PIOd; // PIO data in
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input [15:0] PIOd; // PIO data in
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output [15:0] PIOq; // PIO data out
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output [15:0] PIOq; // PIO data out
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input PIOwe; // PIO direction bit '1'=write, '0'=read
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input PIOwe; // PIO direction bit '1'=write, '0'=read
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reg PIOack;
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reg PIOack;
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// ATA signals
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// ATA signals
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output RESETn;
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output RESETn;
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input [15:0] DDi;
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input [15:0] DDi;
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output [15:0] DDo;
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output [15:0] DDo;
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output DDoe;
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output DDoe;
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output [ 2:0] DA;
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output [ 2:0] DA;
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output CS0n;
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output CS0n;
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output CS1n;
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output CS1n;
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output DIORn;
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output DIORn;
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output DIOWn;
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output DIOWn;
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input IORDY;
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input IORDY;
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input INTRQ;
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input INTRQ;
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reg RESETn;
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reg RESETn;
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reg [15:0] DDo;
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reg [15:0] DDo;
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reg DDoe;
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reg DDoe;
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reg [ 2:0] DA;
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reg [ 2:0] DA;
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reg CS0n;
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reg CS0n;
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reg CS1n;
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reg CS1n;
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reg DIORn;
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reg DIORn;
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reg DIOWn;
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reg DIOWn;
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//
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//
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// signals & variables
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// signals & variables
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//
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//
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wire PIOdone; // PIO timing controller done
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wire PIOdone; // PIO timing controller done
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// PIO signals
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// PIO signals
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wire PIOdior, PIOdiow, PIOoe;
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wire PIOdior, PIOdiow, PIOoe;
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// synchronized ATA inputs
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// synchronized ATA inputs
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reg sIORDY;
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reg sIORDY;
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//
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//
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// module body
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// module body
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//
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//
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// synchronize incoming signals
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// synchronize incoming signals
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reg cIORDY; // capture IORDY
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reg cIORDY; // capture IORDY
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reg cINTRQ; // capture INTRQ
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reg cINTRQ; // capture INTRQ
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|
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always @(posedge clk)
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always @(posedge clk)
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begin : synch_incoming
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begin : synch_incoming
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|
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cIORDY <= #1 IORDY;
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cIORDY <= #1 IORDY;
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cINTRQ <= #1 INTRQ;
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cINTRQ <= #1 INTRQ;
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sIORDY <= #1 cIORDY;
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sIORDY <= #1 cIORDY;
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irq <= #1 cINTRQ;
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irq <= #1 cINTRQ;
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end
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end
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// generate ATA signals
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// generate ATA signals
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (~nReset)
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if (~nReset)
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begin
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begin
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RESETn <= #1 1'b0;
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RESETn <= #1 1'b0;
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DIORn <= #1 1'b1;
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DIORn <= #1 1'b1;
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DIOWn <= #1 1'b1;
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DIOWn <= #1 1'b1;
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DA <= #1 0;
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DA <= #1 0;
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CS0n <= #1 1'b1;
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CS0n <= #1 1'b1;
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CS1n <= #1 1'b1;
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CS1n <= #1 1'b1;
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DDo <= #1 0;
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DDo <= #1 0;
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DDoe <= #1 1'b0;
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DDoe <= #1 1'b0;
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end
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end
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else if (rst)
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else if (rst)
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begin
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begin
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RESETn <= #1 1'b0;
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RESETn <= #1 1'b0;
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DIORn <= #1 1'b1;
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DIORn <= #1 1'b1;
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DIOWn <= #1 1'b1;
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DIOWn <= #1 1'b1;
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DA <= #1 0;
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DA <= #1 0;
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CS0n <= #1 1'b1;
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CS0n <= #1 1'b1;
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CS1n <= #1 1'b1;
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CS1n <= #1 1'b1;
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DDo <= #1 0;
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DDo <= #1 0;
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DDoe <= #1 1'b0;
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DDoe <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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RESETn <= #1 !IDEctrl_rst;
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RESETn <= #1 !IDEctrl_rst;
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DA <= #1 PIOa[2:0];
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DA <= #1 PIOa[2:0];
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CS0n <= #1 !( !PIOa[3] & PIOreq); // CS0 asserted when A(3) = '0'
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CS0n <= #1 !( !PIOa[3] & PIOreq); // CS0 asserted when A(3) = '0'
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CS1n <= #1 !( PIOa[3] & PIOreq); // CS1 asserted when A(3) = '1'
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CS1n <= #1 !( PIOa[3] & PIOreq); // CS1 asserted when A(3) = '1'
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|
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DDo <= #1 PIOd;
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DDo <= #1 PIOd;
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DDoe <= #1 PIOoe;
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DDoe <= #1 PIOoe;
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DIORn <= #1 !PIOdior;
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DIORn <= #1 !PIOdior;
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DIOWn <= #1 !PIOdiow;
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DIOWn <= #1 !PIOdiow;
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end
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end
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// generate selected device
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// generate selected device
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reg SelDev;
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reg SelDev;
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always @(posedge clk)
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always @(posedge clk)
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if (PIOdone & (PIOa == 4'b0110) & PIOwe)
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if (PIOdone & (PIOa == 4'b0110) & PIOwe)
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SelDev <= #1 PIOd[4];
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SelDev <= #1 PIOd[4];
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// generate PIOgo signal
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// generate PIOgo signal
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always @(posedge clk or negedge nReset)
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always @(posedge clk or negedge nReset)
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if (~nReset)
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if (~nReset)
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begin
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begin
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dPIOreq <= #1 1'b0;
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dPIOreq <= #1 1'b0;
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PIOgo <= #1 1'b0;
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PIOgo <= #1 1'b0;
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end
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end
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else if (rst)
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else if (rst)
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begin
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begin
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dPIOreq <= #1 1'b0;
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dPIOreq <= #1 1'b0;
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PIOgo <= #1 1'b0;
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PIOgo <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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dPIOreq <= #1 PIOreq & !PIOack;
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dPIOreq <= #1 PIOreq & !PIOack;
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PIOgo <= #1 (PIOreq & !dPIOreq) & IDEctrl_IDEen;
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PIOgo <= #1 (PIOreq & !dPIOreq) & IDEctrl_IDEen;
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end
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end
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//
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//
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// Hookup PIO access controller
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// Hookup PIO access controller
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//
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//
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atahost_pio_actrl #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)
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atahost_pio_actrl #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)
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PIO_access_control (
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PIO_access_control (
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.clk(clk),
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.clk(clk),
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.nReset(nReset),
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.nReset(nReset),
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.rst(rst),
|
.rst(rst),
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.IDEctrl_FATR0(IDEctrl_FATR0),
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.IDEctrl_FATR0(IDEctrl_FATR0),
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.IDEctrl_FATR1(IDEctrl_FATR1),
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.IDEctrl_FATR1(IDEctrl_FATR1),
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.cmdport_T1(cmdport_T1),
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.cmdport_T1(cmdport_T1),
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.cmdport_T2(cmdport_T2),
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.cmdport_T2(cmdport_T2),
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.cmdport_T4(cmdport_T4),
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.cmdport_T4(cmdport_T4),
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.cmdport_Teoc(cmdport_Teoc),
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.cmdport_Teoc(cmdport_Teoc),
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.cmdport_IORDYen(cmdport_IORDYen),
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.cmdport_IORDYen(cmdport_IORDYen),
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.dport0_T1(dport0_T1),
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.dport0_T1(dport0_T1),
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.dport0_T2(dport0_T2),
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.dport0_T2(dport0_T2),
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.dport0_T4(dport0_T4),
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.dport0_T4(dport0_T4),
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.dport0_Teoc(dport0_Teoc),
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.dport0_Teoc(dport0_Teoc),
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.dport0_IORDYen(dport0_IORDYen),
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.dport0_IORDYen(dport0_IORDYen),
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.dport1_T1(dport1_T1),
|
.dport1_T1(dport1_T1),
|
.dport1_T2(dport1_T2),
|
.dport1_T2(dport1_T2),
|
.dport1_T4(dport1_T4),
|
.dport1_T4(dport1_T4),
|
.dport1_Teoc(dport1_Teoc),
|
.dport1_Teoc(dport1_Teoc),
|
.dport1_IORDYen(dport1_IORDYen),
|
.dport1_IORDYen(dport1_IORDYen),
|
.SelDev(SelDev),
|
.SelDev(SelDev),
|
.go(PIOgo),
|
.go(PIOgo),
|
.done(PIOdone),
|
.done(PIOdone),
|
.dir(PIOwe),
|
.dir(PIOwe),
|
.a(PIOa),
|
.a(PIOa),
|
.q(PIOq),
|
.q(PIOq),
|
.DDi(DDi),
|
.DDi(DDi),
|
.oe(PIOoe),
|
.oe(PIOoe),
|
.DIOR(PIOdior),
|
.DIOR(PIOdior),
|
.DIOW(PIOdiow),
|
.DIOW(PIOdiow),
|
.IORDY(sIORDY)
|
.IORDY(sIORDY)
|
);
|
);
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
PIOack <= #1 PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request)
|
PIOack <= #1 PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request)
|
|
|
endmodule
|
endmodule
|
|
|
