---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- OpenCores IDE Controller ----
|
---- OpenCores IDE Controller ----
|
---- PIO Access Controller (common for OCIDEC 2 and above) ----
|
---- PIO Access Controller (common for OCIDEC 2 and above) ----
|
---- ----
|
---- ----
|
---- Author: Richard Herveille ----
|
---- Author: Richard Herveille ----
|
---- richard@asics.ws ----
|
---- richard@asics.ws ----
|
---- www.asics.ws ----
|
---- www.asics.ws ----
|
---- ----
|
---- ----
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2001, 2002 Richard Herveille ----
|
---- Copyright (C) 2001, 2002 Richard Herveille ----
|
---- richard@asics.ws ---
|
---- richard@asics.ws ---
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
---- restriction provided that this copyright statement is not ----
|
---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer.----
|
---- the original copyright notice and the associated disclaimer.----
|
---- ----
|
---- ----
|
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
|
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
|
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
|
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
|
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
|
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
|
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
|
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
|
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
|
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
|
---- POSSIBILITY OF SUCH DAMAGE. ----
|
---- POSSIBILITY OF SUCH DAMAGE. ----
|
---- ----
|
---- ----
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
|
-- rev.: 1.0 march 9th, 2001
|
-- rev.: 1.0 march 9th, 2001
|
-- rev.: 1.0a april 12th, 2001 Removed references to records.vhd
|
-- rev.: 1.0a april 12th, 2001 Removed references to records.vhd
|
--
|
--
|
--
|
--
|
-- CVS Log
|
-- CVS Log
|
--
|
--
|
-- $Id: atahost_pio_actrl.vhd,v 1.2 2002-05-19 06:07:09 rherveille Exp $
|
-- $Id: atahost_pio_actrl.vhd,v 1.2 2002-05-19 06:07:09 rherveille Exp $
|
--
|
--
|
-- $Date: 2002-05-19 06:07:09 $
|
-- $Date: 2002-05-19 06:07:09 $
|
-- $Revision: 1.2 $
|
-- $Revision: 1.2 $
|
-- $Author: rherveille $
|
-- $Author: rherveille $
|
-- $Locker: $
|
-- $Locker: $
|
-- $State: Exp $
|
-- $State: Exp $
|
--
|
--
|
-- Change History:
|
-- Change History:
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
|
--
|
--
|
---------------------------
|
---------------------------
|
-- PIO Access controller --
|
-- PIO Access controller --
|
---------------------------
|
---------------------------
|
--
|
--
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
|
|
entity atahost_pio_actrl is
|
entity atahost_pio_actrl is
|
generic(
|
generic(
|
TWIDTH : natural := 8; -- counter width
|
TWIDTH : natural := 8; -- counter width
|
|
|
-- PIO mode 0 settings (@100MHz clock)
|
-- PIO mode 0 settings (@100MHz clock)
|
PIO_mode0_T1 : natural := 6; -- 70ns
|
PIO_mode0_T1 : natural := 6; -- 70ns
|
PIO_mode0_T2 : natural := 28; -- 290ns
|
PIO_mode0_T2 : natural := 28; -- 290ns
|
PIO_mode0_T4 : natural := 2; -- 30ns
|
PIO_mode0_T4 : natural := 2; -- 30ns
|
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
|
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
|
);
|
);
|
port(
|
port(
|
clk : in std_logic; -- master clock
|
clk : in std_logic; -- master clock
|
nReset : in std_logic; -- asynchronous active low reset
|
nReset : in std_logic; -- asynchronous active low reset
|
rst : in std_logic; -- synchronous active high reset
|
rst : in std_logic; -- synchronous active high reset
|
|
|
IDEctrl_FATR0,
|
IDEctrl_FATR0,
|
IDEctrl_FATR1 : in std_logic;
|
IDEctrl_FATR1 : in std_logic;
|
|
|
cmdport_T1,
|
cmdport_T1,
|
cmdport_T2,
|
cmdport_T2,
|
cmdport_T4,
|
cmdport_T4,
|
cmdport_Teoc : in unsigned(7 downto 0);
|
cmdport_Teoc : in unsigned(7 downto 0);
|
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
|
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
|
|
|
dport0_T1,
|
dport0_T1,
|
dport0_T2,
|
dport0_T2,
|
dport0_T4,
|
dport0_T4,
|
dport0_Teoc : in unsigned(7 downto 0);
|
dport0_Teoc : in unsigned(7 downto 0);
|
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
|
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
|
|
|
dport1_T1,
|
dport1_T1,
|
dport1_T2,
|
dport1_T2,
|
dport1_T4,
|
dport1_T4,
|
dport1_Teoc : in unsigned(7 downto 0);
|
dport1_Teoc : in unsigned(7 downto 0);
|
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
|
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
|
|
|
SelDev : in std_logic; -- Selected device
|
SelDev : in std_logic; -- Selected device
|
|
|
go : in std_logic; -- Start transfer sequence
|
go : in std_logic; -- Start transfer sequence
|
done : out std_logic; -- Transfer sequence done
|
done : out std_logic; -- Transfer sequence done
|
dir : in std_logic; -- Transfer direction '1'=write, '0'=read
|
dir : in std_logic; -- Transfer direction '1'=write, '0'=read
|
a : in unsigned(3 downto 0); -- PIO transfer address
|
a : in unsigned(3 downto 0); -- PIO transfer address
|
q : out std_logic_vector(15 downto 0); -- Data read from ATA devices
|
q : out std_logic_vector(15 downto 0); -- Data read from ATA devices
|
|
|
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
|
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
|
oe : buffer std_logic; -- DDbus output-enable signal
|
oe : buffer std_logic; -- DDbus output-enable signal
|
|
|
DIOR,
|
DIOR,
|
DIOW : buffer std_logic;
|
DIOW : buffer std_logic;
|
IORDY : in std_logic
|
IORDY : in std_logic
|
);
|
);
|
end entity atahost_pio_actrl;
|
end entity atahost_pio_actrl;
|
|
|
architecture structural of atahost_pio_actrl is
|
architecture structural of atahost_pio_actrl is
|
--
|
--
|
-- Component declarations
|
-- Component declarations
|
--
|
--
|
component atahost_pio_tctrl is
|
component atahost_pio_tctrl is
|
generic(
|
generic(
|
TWIDTH : natural := 8; -- counter width
|
TWIDTH : natural := 8; -- counter width
|
|
|
-- PIO mode 0 settings (@100MHz clock)
|
-- PIO mode 0 settings (@100MHz clock)
|
PIO_mode0_T1 : natural := 6; -- 70ns
|
PIO_mode0_T1 : natural := 6; -- 70ns
|
PIO_mode0_T2 : natural := 28; -- 290ns
|
PIO_mode0_T2 : natural := 28; -- 290ns
|
PIO_mode0_T4 : natural := 2; -- 30ns
|
PIO_mode0_T4 : natural := 2; -- 30ns
|
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
|
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
|
);
|
);
|
port(
|
port(
|
clk : in std_logic; -- master clock
|
clk : in std_logic; -- master clock
|
nReset : in std_logic; -- asynchronous active low reset
|
nReset : in std_logic; -- asynchronous active low reset
|
rst : in std_logic; -- synchronous active high reset
|
rst : in std_logic; -- synchronous active high reset
|
|
|
-- timing/control register settings
|
-- timing/control register settings
|
IORDY_en : in std_logic; -- use IORDY (or not)
|
IORDY_en : in std_logic; -- use IORDY (or not)
|
T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks)
|
T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks)
|
T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks)
|
T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks)
|
T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks)
|
T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks)
|
Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time
|
Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time
|
|
|
-- control signals
|
-- control signals
|
go : in std_logic; -- PIO controller selected (strobe signal)
|
go : in std_logic; -- PIO controller selected (strobe signal)
|
we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device
|
we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device
|
|
|
-- return signals
|
-- return signals
|
oe : buffer std_logic; -- output enable signal
|
oe : buffer std_logic; -- output enable signal
|
done : out std_logic; -- finished cycle
|
done : out std_logic; -- finished cycle
|
dstrb : out std_logic; -- data strobe, latch data (during read)
|
dstrb : out std_logic; -- data strobe, latch data (during read)
|
|
|
-- ATA signals
|
-- ATA signals
|
DIOR, -- IOread signal, active high
|
DIOR, -- IOread signal, active high
|
DIOW : buffer std_logic; -- IOwrite signal, active high
|
DIOW : buffer std_logic; -- IOwrite signal, active high
|
IORDY : in std_logic -- IORDY signal
|
IORDY : in std_logic -- IORDY signal
|
);
|
);
|
end component atahost_pio_tctrl;
|
end component atahost_pio_tctrl;
|
|
|
signal dstrb : std_logic;
|
signal dstrb : std_logic;
|
signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0);
|
signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0);
|
signal IORDYen : std_logic;
|
signal IORDYen : std_logic;
|
|
|
begin
|
begin
|
--
|
--
|
--------------------------
|
--------------------------
|
-- PIO transfer control --
|
-- PIO transfer control --
|
--------------------------
|
--------------------------
|
--
|
--
|
-- capture ATA data for PIO access
|
-- capture ATA data for PIO access
|
gen_PIOq: process(clk)
|
gen_PIOq: process(clk)
|
begin
|
begin
|
if (clk'event and clk = '1') then
|
if (clk'event and clk = '1') then
|
if (dstrb = '1') then
|
if (dstrb = '1') then
|
q <= DDi;
|
q <= DDi;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process gen_PIOq;
|
end process gen_PIOq;
|
|
|
--
|
--
|
-- PIO timing controllers
|
-- PIO timing controllers
|
--
|
--
|
|
|
-- select timing settings for the addressed port
|
-- select timing settings for the addressed port
|
sel_port_t: process(clk)
|
sel_port_t: process(clk)
|
variable Asel : std_logic; -- address selected
|
variable Asel : std_logic; -- address selected
|
variable iT1, iT2, iT4, iTeoc : unsigned(TWIDTH -1 downto 0);
|
variable iT1, iT2, iT4, iTeoc : unsigned(TWIDTH -1 downto 0);
|
variable iIORDYen : std_logic;
|
variable iIORDYen : std_logic;
|
begin
|
begin
|
-- initially set timing registers to compatible timing
|
-- initially set timing registers to compatible timing
|
iT1 := cmdport_T1;
|
iT1 := cmdport_T1;
|
iT2 := cmdport_T2;
|
iT2 := cmdport_T2;
|
iT4 := cmdport_T4;
|
iT4 := cmdport_T4;
|
iTeoc := cmdport_Teoc;
|
iTeoc := cmdport_Teoc;
|
iIORDYen := cmdport_IORDYen;
|
iIORDYen := cmdport_IORDYen;
|
|
|
-- detect data-port access
|
-- detect data-port access
|
Asel := not a(3) and not a(2) and not a(1) and not a(0); -- data port
|
Asel := not a(3) and not a(2) and not a(1) and not a(0); -- data port
|
if (Asel = '1') then -- data port selected, 16bit transfers
|
if (Asel = '1') then -- data port selected, 16bit transfers
|
if ((SelDev = '1') and (IDEctrl_FATR1 = '1')) then -- data port1 selected and enabled ?
|
if ((SelDev = '1') and (IDEctrl_FATR1 = '1')) then -- data port1 selected and enabled ?
|
iT1 := dport1_T1;
|
iT1 := dport1_T1;
|
iT2 := dport1_T2;
|
iT2 := dport1_T2;
|
iT4 := dport1_T4;
|
iT4 := dport1_T4;
|
iTeoc := dport1_Teoc;
|
iTeoc := dport1_Teoc;
|
iIORDYen := dport1_IORDYen;
|
iIORDYen := dport1_IORDYen;
|
elsif((SelDev = '0') and (IDEctrl_FATR0 = '1')) then -- data port0 selected and enabled ?
|
elsif((SelDev = '0') and (IDEctrl_FATR0 = '1')) then -- data port0 selected and enabled ?
|
iT1 := dport0_T1;
|
iT1 := dport0_T1;
|
iT2 := dport0_T2;
|
iT2 := dport0_T2;
|
iT4 := dport0_T4;
|
iT4 := dport0_T4;
|
iTeoc := dport0_Teoc;
|
iTeoc := dport0_Teoc;
|
iIORDYen := dport0_IORDYen;
|
iIORDYen := dport0_IORDYen;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if (clk'event and clk = '1') then
|
if (clk'event and clk = '1') then
|
T1 <= iT1;
|
T1 <= iT1;
|
T2 <= iT2;
|
T2 <= iT2;
|
T4 <= iT4;
|
T4 <= iT4;
|
Teoc <= iTeoc;
|
Teoc <= iTeoc;
|
IORDYen <= iIORDYen;
|
IORDYen <= iIORDYen;
|
end if;
|
end if;
|
end process sel_port_t;
|
end process sel_port_t;
|
|
|
--
|
--
|
-- hookup timing controller
|
-- hookup timing controller
|
--
|
--
|
PIO_timing_controller: atahost_pio_tctrl
|
PIO_timing_controller: atahost_pio_tctrl
|
generic map (
|
generic map (
|
TWIDTH => TWIDTH,
|
TWIDTH => TWIDTH,
|
PIO_mode0_T1 => PIO_mode0_T1,
|
PIO_mode0_T1 => PIO_mode0_T1,
|
PIO_mode0_T2 => PIO_mode0_T2,
|
PIO_mode0_T2 => PIO_mode0_T2,
|
PIO_mode0_T4 => PIO_mode0_T4,
|
PIO_mode0_T4 => PIO_mode0_T4,
|
PIO_mode0_Teoc => PIO_mode0_Teoc
|
PIO_mode0_Teoc => PIO_mode0_Teoc
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
nReset => nReset,
|
nReset => nReset,
|
rst => rst,
|
rst => rst,
|
IORDY_en => IORDYen,
|
IORDY_en => IORDYen,
|
T1 => T1,
|
T1 => T1,
|
T2 => T2,
|
T2 => T2,
|
T4 => T4,
|
T4 => T4,
|
Teoc => Teoc,
|
Teoc => Teoc,
|
go => go,
|
go => go,
|
we => dir,
|
we => dir,
|
oe => oe,
|
oe => oe,
|
done => done,
|
done => done,
|
dstrb => dstrb,
|
dstrb => dstrb,
|
DIOR => dior,
|
DIOR => dior,
|
DIOW => diow,
|
DIOW => diow,
|
IORDY => IORDY
|
IORDY => IORDY
|
);
|
);
|
end architecture structural;
|
end architecture structural;
|
|
|
|
|
