---------------------------------------------------------------------
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---------------------------------------------------------------------
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---- ----
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---- ----
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---- Run-Once Counter ----
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---- Run-Once Counter ----
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---- ----
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---- ----
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---- Author: Richard Herveille ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- www.asics.ws ----
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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2001, 2002 Richard Herveille ----
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---- Copyright (C) 2001, 2002 Richard Herveille ----
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---- richard@asics.ws ----
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---- richard@asics.ws ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer.----
|
---- the original copyright notice and the associated disclaimer.----
|
---- ----
|
---- ----
|
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
|
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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|
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--
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--
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-- CVS Log
|
-- CVS Log
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--
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--
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-- $Id: ro_cnt.vhd,v 1.1 2002-03-01 03:49:03 rherveille Exp $
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-- $Id: ro_cnt.vhd,v 1.1 2002-03-01 03:49:03 rherveille Exp $
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--
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--
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-- $Date: 2002-03-01 03:49:03 $
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-- $Date: 2002-03-01 03:49:03 $
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-- $Revision: 1.1 $
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-- $Revision: 1.1 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
|
--
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--
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-- Change History:
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-- Change History:
|
-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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|
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entity ro_cnt is
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entity ro_cnt is
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generic(
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generic(
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SIZE : natural := 8;
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SIZE : natural := 8;
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UD : std_logic := '0'; -- default count down
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UD : std_logic := '0'; -- default count down
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ID : natural := 0 -- initial data after reset
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ID : natural := 0 -- initial data after reset
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);
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);
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port(
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port(
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clk : in std_logic; -- master clock
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clk : in std_logic; -- master clock
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nReset : in std_logic := '1'; -- asynchronous active low reset
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nReset : in std_logic := '1'; -- asynchronous active low reset
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rst : in std_logic := '0'; -- synchronous active high reset
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rst : in std_logic := '0'; -- synchronous active high reset
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|
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cnt_en : in std_logic := '1'; -- count enable
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cnt_en : in std_logic := '1'; -- count enable
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go : in std_logic; -- load counter and start sequence
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go : in std_logic; -- load counter and start sequence
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done : out std_logic; -- done counting
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done : out std_logic; -- done counting
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d : in unsigned(SIZE -1 downto 0); -- load counter value
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d : in unsigned(SIZE -1 downto 0); -- load counter value
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q : out unsigned(SIZE -1 downto 0) -- current counter value
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q : out unsigned(SIZE -1 downto 0) -- current counter value
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);
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);
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end entity ro_cnt;
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end entity ro_cnt;
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|
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architecture structural of ro_cnt is
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architecture structural of ro_cnt is
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component ud_cnt is
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component ud_cnt is
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generic(
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generic(
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SIZE : natural := 8;
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SIZE : natural := 8;
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RESD : natural := 0 -- initial data after reset
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RESD : natural := 0 -- initial data after reset
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);
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);
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port(
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port(
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clk : in std_logic; -- master clock
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clk : in std_logic; -- master clock
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nReset : in std_logic := '1'; -- asynchronous active low reset
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nReset : in std_logic := '1'; -- asynchronous active low reset
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rst : in std_logic := '0'; -- synchronous active high reset
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rst : in std_logic := '0'; -- synchronous active high reset
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|
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cnt_en : in std_logic := '1'; -- count enable
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cnt_en : in std_logic := '1'; -- count enable
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ud : in std_logic := '0'; -- up / not down
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ud : in std_logic := '0'; -- up / not down
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nld : in std_logic := '1'; -- synchronous active low load
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nld : in std_logic := '1'; -- synchronous active low load
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d : in unsigned(SIZE -1 downto 0); -- load counter value
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d : in unsigned(SIZE -1 downto 0); -- load counter value
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q : out unsigned(SIZE -1 downto 0); -- current counter value
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q : out unsigned(SIZE -1 downto 0); -- current counter value
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|
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rci : in std_logic := '1'; -- carry input
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rci : in std_logic := '1'; -- carry input
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rco : out std_logic -- carry output
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rco : out std_logic -- carry output
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);
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);
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end component ud_cnt;
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end component ud_cnt;
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|
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signal rci, rco, nld : std_logic;
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signal rci, rco, nld : std_logic;
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begin
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begin
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gen_ctrl: process(clk, nReset)
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gen_ctrl: process(clk, nReset)
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begin
|
begin
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if (nReset = '0') then
|
if (nReset = '0') then
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rci <= '0';
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rci <= '0';
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elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
|
if (rst = '1') then
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if (rst = '1') then
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rci <= '0';
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rci <= '0';
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else
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else
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rci <= go or (rci and not rco);
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rci <= go or (rci and not rco);
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end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
nld <= not go;
|
nld <= not go;
|
|
|
-- hookup counter
|
-- hookup counter
|
cnt : ud_cnt
|
cnt : ud_cnt
|
generic map (
|
generic map (
|
SIZE => SIZE,
|
SIZE => SIZE,
|
RESD => ID
|
RESD => ID
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
nReset => nReset,
|
nReset => nReset,
|
rst => rst,
|
rst => rst,
|
cnt_en => cnt_en,
|
cnt_en => cnt_en,
|
ud => UD,
|
ud => UD,
|
nld => nld,
|
nld => nld,
|
D => D,
|
D => D,
|
Q => Q,
|
Q => Q,
|
rci => rci,
|
rci => rci,
|
rco => rco
|
rco => rco
|
);
|
);
|
|
|
done <= rco;
|
done <= rco;
|
end architecture structural;
|
end architecture structural;
|
|
|
