---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- OpenCores IDE Controller ----
|
---- OpenCores IDE Controller ----
|
---- synchronous single clock fifo, uses LFSR pointers ----
|
---- synchronous single clock fifo, uses LFSR pointers ----
|
---- ----
|
---- ----
|
---- Author: Richard Herveille ----
|
---- Author: Richard Herveille ----
|
---- richard@asics.ws ----
|
---- richard@asics.ws ----
|
---- www.asics.ws ----
|
---- www.asics.ws ----
|
---- ----
|
---- ----
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2001, 2002 Richard Herveille ----
|
---- Copyright (C) 2001, 2002 Richard Herveille ----
|
---- richard@asics.ws ----
|
---- richard@asics.ws ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
---- restriction provided that this copyright statement is not ----
|
---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer.----
|
---- the original copyright notice and the associated disclaimer.----
|
---- ----
|
---- ----
|
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
|
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
|
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
|
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
|
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
|
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
|
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
|
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
|
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
|
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
|
---- POSSIBILITY OF SUCH DAMAGE. ----
|
---- POSSIBILITY OF SUCH DAMAGE. ----
|
---- ----
|
---- ----
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
|
-- rev.: 1.0 march 12th, 2001. Initial release
|
-- rev.: 1.0 march 12th, 2001. Initial release
|
--
|
--
|
-- CVS Log
|
-- CVS Log
|
--
|
--
|
-- $Id: atahost_fifo.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
|
-- $Id: atahost_fifo.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $
|
--
|
--
|
-- $Date: 2002-02-18 14:32:12 $
|
-- $Date: 2002-02-18 14:32:12 $
|
-- $Revision: 1.1 $
|
-- $Revision: 1.1 $
|
-- $Author: rherveille $
|
-- $Author: rherveille $
|
-- $Locker: $
|
-- $Locker: $
|
-- $State: Exp $
|
-- $State: Exp $
|
--
|
--
|
-- Change History:
|
-- Change History:
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
--
|
--
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
|
|
entity atahost_fifo is
|
entity atahost_fifo is
|
generic(
|
generic(
|
DEPTH : natural := 31; -- fifo depth, this must be a number according to the following range
|
DEPTH : natural := 31; -- fifo depth, this must be a number according to the following range
|
-- 3, 7, 15, 31, 63 ... 65535
|
-- 3, 7, 15, 31, 63 ... 65535
|
SIZE : natural := 32 -- data width
|
SIZE : natural := 32 -- data width
|
);
|
);
|
port(
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port(
|
clk : in std_logic; -- master clock in
|
clk : in std_logic; -- master clock in
|
nReset : in std_logic := '1'; -- asynchronous active low reset
|
nReset : in std_logic := '1'; -- asynchronous active low reset
|
rst : in std_logic := '0'; -- synchronous active high reset
|
rst : in std_logic := '0'; -- synchronous active high reset
|
|
|
rreq : in std_logic; -- read request
|
rreq : in std_logic; -- read request
|
wreq : in std_logic; -- write request
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wreq : in std_logic; -- write request
|
|
|
empty : out std_logic; -- fifo empty
|
empty : out std_logic; -- fifo empty
|
full : out std_logic; -- fifo full
|
full : out std_logic; -- fifo full
|
|
|
D : in std_logic_vector(SIZE -1 downto 0); -- data input
|
D : in std_logic_vector(SIZE -1 downto 0); -- data input
|
Q : out std_logic_vector(SIZE -1 downto 0) -- data output
|
Q : out std_logic_vector(SIZE -1 downto 0) -- data output
|
);
|
);
|
end entity atahost_fifo;
|
end entity atahost_fifo;
|
|
|
architecture structural of atahost_fifo is
|
architecture structural of atahost_fifo is
|
--
|
--
|
-- function declarations
|
-- function declarations
|
--
|
--
|
function bitsize(n : in natural) return natural is
|
function bitsize(n : in natural) return natural is
|
variable tmp : unsigned(32 downto 1);
|
variable tmp : unsigned(32 downto 1);
|
variable cnt : integer;
|
variable cnt : integer;
|
begin
|
begin
|
tmp := conv_unsigned(n, 32);
|
tmp := conv_unsigned(n, 32);
|
cnt := 32;
|
cnt := 32;
|
|
|
while ( (tmp(cnt) = '0') and (cnt > 0) ) loop
|
while ( (tmp(cnt) = '0') and (cnt > 0) ) loop
|
cnt := cnt -1;
|
cnt := cnt -1;
|
end loop;
|
end loop;
|
|
|
return natural(cnt);
|
return natural(cnt);
|
end function bitsize;
|
end function bitsize;
|
|
|
--
|
--
|
-- component declarations
|
-- component declarations
|
--
|
--
|
component atahost_lfsr is
|
component atahost_lfsr is
|
generic(
|
generic(
|
TAPS : positive range 16 downto 3 :=8;
|
TAPS : positive range 16 downto 3 :=8;
|
OFFSET : natural := 0
|
OFFSET : natural := 0
|
);
|
);
|
port(
|
port(
|
clk : in std_logic; -- clock input
|
clk : in std_logic; -- clock input
|
ena : in std_logic; -- count enable
|
ena : in std_logic; -- count enable
|
nReset : in std_logic; -- asynchronous active low reset
|
nReset : in std_logic; -- asynchronous active low reset
|
rst : in std_logic; -- synchronous active high reset
|
rst : in std_logic; -- synchronous active high reset
|
|
|
Q : out unsigned(TAPS downto 1); -- count value
|
Q : out unsigned(TAPS downto 1); -- count value
|
Qprev : out unsigned(TAPS downto 1) -- previous count value
|
Qprev : out unsigned(TAPS downto 1) -- previous count value
|
);
|
);
|
end component atahost_lfsr;
|
end component atahost_lfsr;
|
|
|
constant ADEPTH : natural := bitsize(DEPTH);
|
constant ADEPTH : natural := bitsize(DEPTH);
|
|
|
-- memory block
|
-- memory block
|
type memory is array (DEPTH -1 downto 0) of std_logic_vector(SIZE -1 downto 0);
|
type memory is array (DEPTH -1 downto 0) of std_logic_vector(SIZE -1 downto 0);
|
-- shared variable mem : memory; -- VHDL'93 PREFERED
|
-- shared variable mem : memory; -- VHDL'93 PREFERED
|
signal mem : memory; -- VHDL'87
|
signal mem : memory; -- VHDL'87
|
|
|
-- address pointers
|
-- address pointers
|
signal wr_ptr, rd_ptr, dwr_ptr, drd_ptr : unsigned(ADEPTH -1 downto 0);
|
signal wr_ptr, rd_ptr, dwr_ptr, drd_ptr : unsigned(ADEPTH -1 downto 0);
|
|
|
begin
|
begin
|
-- generate write address; hookup write_pointer counter
|
-- generate write address; hookup write_pointer counter
|
wr_ptr_lfsr: atahost_lfsr
|
wr_ptr_lfsr: atahost_lfsr
|
generic map(
|
generic map(
|
TAPS => ADEPTH,
|
TAPS => ADEPTH,
|
OFFSET => 0
|
OFFSET => 0
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
ena => wreq,
|
ena => wreq,
|
nReset => nReset,
|
nReset => nReset,
|
rst => rst,
|
rst => rst,
|
Q => wr_ptr,
|
Q => wr_ptr,
|
Qprev => dwr_ptr
|
Qprev => dwr_ptr
|
);
|
);
|
|
|
-- generate read address; hookup read_pointer counter
|
-- generate read address; hookup read_pointer counter
|
rd_ptr_lfsr: atahost_lfsr
|
rd_ptr_lfsr: atahost_lfsr
|
generic map(
|
generic map(
|
TAPS => ADEPTH,
|
TAPS => ADEPTH,
|
OFFSET => 0
|
OFFSET => 0
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
ena => rreq,
|
ena => rreq,
|
nReset => nReset,
|
nReset => nReset,
|
rst => rst,
|
rst => rst,
|
Q => rd_ptr,
|
Q => rd_ptr,
|
Qprev => drd_ptr
|
Qprev => drd_ptr
|
);
|
);
|
|
|
-- generate full/empty signal
|
-- generate full/empty signal
|
full <= '1' when (wr_ptr = drd_ptr) else '0';
|
full <= '1' when (wr_ptr = drd_ptr) else '0';
|
empty <= '1' when (rd_ptr = wr_ptr) else '0';
|
empty <= '1' when (rd_ptr = wr_ptr) else '0';
|
|
|
-- generate memory structure
|
-- generate memory structure
|
gen_mem: process(clk)
|
gen_mem: process(clk)
|
begin
|
begin
|
if (clk'event and clk = '1') then
|
if (clk'event and clk = '1') then
|
if (wreq = '1') then
|
if (wreq = '1') then
|
mem(conv_integer(wr_ptr)) <= D;
|
mem(conv_integer(wr_ptr)) <= D;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process gen_mem;
|
end process gen_mem;
|
Q <= mem(conv_integer(rd_ptr));
|
Q <= mem(conv_integer(rd_ptr));
|
end architecture structural;
|
end architecture structural;
|
|
|
