###############################################################################
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###############################################################################
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#
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#
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# Pre Synthesis Script
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# Pre Synthesis Script
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#
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#
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# This script only reads in the design and saves it in a DB file
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# This script only reads in the design and saves it in a DB file
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#
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#
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# Author: Rudolf Usselmann
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# Author: Rudolf Usselmann
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# rudi@asics.ws
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# rudi@asics.ws
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#
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#
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# Revision:
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# Revision:
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# 3/7/01 RU Initial Sript
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# 3/7/01 RU Initial Sript
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#
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#
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#
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#
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###############################################################################
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###############################################################################
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# ==============================================
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# ==============================================
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# Setup Design Parameters
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# Setup Design Parameters
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source ../bin/design_spec.dc
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source ../bin/design_spec.dc
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# ==============================================
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# ==============================================
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# Setup Libraries
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# Setup Libraries
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source ../bin/lib_spec.dc
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source ../bin/lib_spec.dc
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# ==============================================
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# ==============================================
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# Setup IO Files
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# Setup IO Files
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append log_file ../log/$active_design "_pre.log"
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append log_file ../log/$active_design "_pre.log"
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append pre_comp_db_file ../out/$design_name "_pre.db"
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append pre_comp_db_file ../out/$design_name "_pre.db"
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sh rm -f $log_file
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sh rm -f $log_file
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# ==============================================
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# ==============================================
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# Setup Misc Variables
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# Setup Misc Variables
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set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
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set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
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# ==============================================
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# ==============================================
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# Read Design
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# Read Design
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echo "+++++++++ Analyzing all design files ..." >> $log_file
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echo "+++++++++ Analyzing all design files ..." >> $log_file
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foreach module $design_files {
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foreach module $design_files {
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echo "+++++++++ Reading: $module" >> $log_file
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echo "+++++++++ Reading: $module" >> $log_file
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echo +++++++++ Reading: $module
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echo +++++++++ Reading: $module
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set module_file_name ""
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set module_file_name ""
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append module_file_name $module ".v"
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append module_file_name $module ".v"
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analyze -f verilog $module_file_name >> $log_file
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analyze -f verilog $module_file_name >> $log_file
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elaborate $module >> $log_file
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elaborate $module >> $log_file
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}
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}
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current_design $active_design
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current_design $active_design
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echo "+++++++++ Linking Design ..." >> $log_file
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echo "+++++++++ Linking Design ..." >> $log_file
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link >> $log_file
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link >> $log_file
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echo "+++++++++ Uniquifying Design ..." >> $log_file
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echo "+++++++++ Uniquifying Design ..." >> $log_file
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uniquify >> $log_file
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uniquify >> $log_file
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echo "+++++++++ Checking Design ..." >> $log_file
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echo "+++++++++ Checking Design ..." >> $log_file
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check_design >> $log_file
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check_design >> $log_file
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# ==============================================
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# ==============================================
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# Save Design
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# Save Design
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echo "+++++++++ Saving Design ..." >> $log_file
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echo "+++++++++ Saving Design ..." >> $log_file
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write_file -hierarchy -format db -output $pre_comp_db_file
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write_file -hierarchy -format db -output $pre_comp_db_file
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