-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- This file is part of the project avs_aes
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-- This file is part of the project avs_aes
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-- see: http://opencores.org/project,avs_aes
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-- see: http://opencores.org/project,avs_aes
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--
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--
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-- description:
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-- description:
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-- Statemachine controlling the encryption datapath within aes_core.vhd does no
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-- Statemachine controlling the encryption datapath within aes_core.vhd does no
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-- dataprocessing itself but only set enables and multiplexer selector ports
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-- dataprocessing itself but only set enables and multiplexer selector ports
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--
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--
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-- Author(s):
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-- Author(s):
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-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
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-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Copyright (c) 2009, Thomas Ruschival
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-- Copyright (c) 2009, Thomas Ruschival
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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-- are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright notice,
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-- * Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright notice,
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-- * Redistributions in binary form must reproduce the above copyright notice,
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-- this list of conditions and the following disclaimer in the documentation
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-- this list of conditions and the following disclaimer in the documentation
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-- and/or other materials provided with the distribution.
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-- and/or other materials provided with the distribution.
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-- * Neither the name of the nor the names of its contributors
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-- * Neither the name of the nor the names of its contributors
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-- may be used to endorse or promote products derived from this software without
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-- may be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- specific prior written permission.
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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-- THE POSSIBILITY OF SUCH DAMAGE
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-- THE POSSIBILITY OF SUCH DAMAGE
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- version management:
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-- version management:
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-- $Author$
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-- $Author:: $
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-- $Date$
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-- $Date:: $
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-- $Revision$
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-- $Revision:: $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library avs_aes_lib;
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library avs_aes_lib;
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use avs_aes_lib.avs_aes_pkg.all;
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use avs_aes_lib.avs_aes_pkg.all;
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entity aes_fsm_encrypt is
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entity aes_fsm_encrypt is
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generic (
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generic (
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NO_ROUNDS : NATURAL := 10); -- number of rounds
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NO_ROUNDS : NATURAL := 10); -- number of rounds
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port (
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port (
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clk : in STD_LOGIC; -- System clock
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clk : in STD_LOGIC; -- System clock
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data_stable : in STD_LOGIC; -- flag valid data/activate the process
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data_stable : in STD_LOGIC; -- flag valid data/activate the process
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-- interface for keygenerator
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-- interface for keygenerator
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key_ready : in STD_LOGIC; -- flag valid roundkeys
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key_ready : in STD_LOGIC; -- flag valid roundkeys
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round_index_out : out NIBBLE; -- address for roundkeys memory
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round_index_out : out NIBBLE; -- address for roundkeys memory
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-- Result of Process
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-- Result of Process
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finished : out STD_LOGIC; -- flag valid result
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finished : out STD_LOGIC; -- flag valid result
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-- Control ports for the Core
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-- Control ports for the Core
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round_type_sel : out STD_LOGIC_VECTOR(1 downto 0) -- selector for mux around mixcols
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round_type_sel : out STD_LOGIC_VECTOR(1 downto 0) -- selector for mux around mixcols
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);
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);
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end entity aes_fsm_encrypt;
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end entity aes_fsm_encrypt;
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--
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--
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architecture Arch1 of AES_FSM_ENCRYPT is
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architecture Arch1 of AES_FSM_ENCRYPT is
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-- types for the FSM
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-- types for the FSM
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type AESstates is (WAIT_KEY, WAIT_DATA, INITIAL_ROUND, DO_ROUND, FINAL_ROUND);
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type AESstates is (WAIT_KEY, WAIT_DATA, INITIAL_ROUND, DO_ROUND, FINAL_ROUND);
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-- FSM signals
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-- FSM signals
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signal FSM : AESstates; -- current state
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signal FSM : AESstates; -- current state
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signal next_FSM : AESstates; -- combinational next state
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signal next_FSM : AESstates; -- combinational next state
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-- Round Counter & address for keygenerate
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-- Round Counter & address for keygenerate
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signal round_index : NIBBLE; -- currently processed round
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signal round_index : NIBBLE; -- currently processed round
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signal next_round_index : NIBBLE; -- next round, index for keygenerate
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signal next_round_index : NIBBLE; -- next round, index for keygenerate
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begin
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begin
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- assign internal values to interface ports
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-- assign internal values to interface ports
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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round_index_out <= next_round_index; -- roundkey address
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round_index_out <= next_round_index; -- roundkey address
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-- purpose: combinational generation of next state for encrytion FSM
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-- purpose: combinational generation of next state for encrytion FSM
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-- type : sequential
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-- type : sequential
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-- inputs : FSM, data_stable, key_ready, round_index
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-- inputs : FSM, data_stable, key_ready, round_index
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-- outputs: next_FSM
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-- outputs: next_FSM
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gen_next_fsm : process (FSM, data_stable, key_ready, round_index) is
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gen_next_fsm : process (FSM, data_stable, key_ready, round_index) is
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begin -- process gen_next_fsm
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begin -- process gen_next_fsm
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case FSM is
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case FSM is
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when WAIT_KEY =>
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when WAIT_KEY =>
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if key_ready = '1' then
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if key_ready = '1' then
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next_FSM <= WAIT_DATA;
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next_FSM <= WAIT_DATA;
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else
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else
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next_FSM <= WAIT_KEY;
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next_FSM <= WAIT_KEY;
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end if;
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end if;
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when WAIT_DATA =>
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when WAIT_DATA =>
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if data_stable = '1' then
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if data_stable = '1' then
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next_FSM <= INITIAL_ROUND;
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next_FSM <= INITIAL_ROUND;
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else
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else
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next_FSM <= WAIT_DATA;
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next_FSM <= WAIT_DATA;
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end if;
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end if;
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when INITIAL_ROUND =>
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when INITIAL_ROUND =>
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next_FSM <= DO_ROUND;
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next_FSM <= DO_ROUND;
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when DO_ROUND =>
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when DO_ROUND =>
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if round_index = STD_LOGIC_VECTOR(to_unsigned(NO_ROUNDS-1, 4)) then
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if round_index = STD_LOGIC_VECTOR(to_unsigned(NO_ROUNDS-1, 4)) then
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next_FSM <= FINAL_ROUND;
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next_FSM <= FINAL_ROUND;
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else
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else
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next_FSM <= DO_ROUND;
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next_FSM <= DO_ROUND;
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end if;
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end if;
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when FINAL_ROUND =>
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when FINAL_ROUND =>
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next_FSM <= WAIT_DATA;
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next_FSM <= WAIT_DATA;
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-- pragma synthesis_off
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-- pragma synthesis_off
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when others =>
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when others =>
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report "FSM in strange state - aborting" severity error;
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report "FSM in strange state - aborting" severity error;
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next_FSM <= WAIT_KEY;
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next_FSM <= WAIT_KEY;
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-- pragma synthesis_on
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-- pragma synthesis_on
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end case;
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end case;
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-- Default behaviour in case key is invalid
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-- Default behaviour in case key is invalid
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if key_ready = '0' then
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if key_ready = '0' then
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next_FSM <= WAIT_KEY;
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next_FSM <= WAIT_KEY;
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end if;
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end if;
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end process gen_next_fsm;
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end process gen_next_fsm;
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-- purpose: assign outputs for encryption
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-- purpose: assign outputs for encryption
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-- type : combinational
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-- type : combinational
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-- inputs : FSM
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-- inputs : FSM
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com_output_assign : process (FSM, round_index) is
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com_output_assign : process (FSM, round_index) is
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begin -- process com_output_assign
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begin -- process com_output_assign
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-- save defaults for encrypt_FSM
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-- save defaults for encrypt_FSM
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round_type_sel <= "00"; -- signal initial_round
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round_type_sel <= "00"; -- signal initial_round
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next_round_index <= round_index;
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next_round_index <= round_index;
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finished <= '0';
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finished <= '0';
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case FSM is
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case FSM is
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when WAIT_KEY =>
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when WAIT_KEY =>
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next_round_index <= X"0";
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next_round_index <= X"0";
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when WAIT_DATA =>
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when WAIT_DATA =>
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next_round_index <= X"0";
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next_round_index <= X"0";
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when INITIAL_ROUND =>
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when INITIAL_ROUND =>
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round_type_sel <= "00"; -- data_in as input to AddKey
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round_type_sel <= "00"; -- data_in as input to AddKey
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-- data is stable, FSM will switch to DO_ROUND in next cycle
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-- data is stable, FSM will switch to DO_ROUND in next cycle
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next_round_index <= X"1"; -- start DO_ROUND with 1st expanded key
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next_round_index <= X"1"; -- start DO_ROUND with 1st expanded key
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when DO_ROUND =>
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when DO_ROUND =>
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round_type_sel <= "01";
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round_type_sel <= "01";
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next_round_index <= STD_LOGIC_VECTOR(UNSIGNED(round_index)+1);
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next_round_index <= STD_LOGIC_VECTOR(UNSIGNED(round_index)+1);
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when FINAL_ROUND =>
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when FINAL_ROUND =>
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-- select signal around mixcols
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-- select signal around mixcols
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round_type_sel <= "10";
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round_type_sel <= "10";
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next_round_index <= X"0";
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next_round_index <= X"0";
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finished <= '1';
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finished <= '1';
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end process com_output_assign;
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end process com_output_assign;
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-- purpose: clocked FSM for encryption
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-- purpose: clocked FSM for encryption
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-- type : sequential
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-- type : sequential
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-- inputs : clk, res_n
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-- inputs : clk, res_n
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clocked_FSM : process (clk) is
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clocked_FSM : process (clk) is
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begin -- process clocked_FSM
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begin -- process clocked_FSM
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if rising_edge(clk) then -- rising clock edge
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if rising_edge(clk) then -- rising clock edge
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FSM <= next_FSM;
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FSM <= next_FSM;
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round_index <= next_round_index;
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round_index <= next_round_index;
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end if;
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end if;
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end process clocked_FSM;
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end process clocked_FSM;
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end architecture Arch1;
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end architecture Arch1;
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