/*
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/*
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This file is part of the AXI4 Transactor and Bus Functional Model
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This file is part of the AXI4 Transactor and Bus Functional Model
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(axi4_tlm_bfm) project:
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(axi4_tlm_bfm) project:
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http://www.opencores.org/project,axi4_tlm_bfm
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http://www.opencores.org/project,axi4_tlm_bfm
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Description
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Description
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Implementation of AXI4 Master BFM core according to AXI4 protocol
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Implementation of AXI4 Master BFM core according to AXI4 protocol
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specification document.
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specification document.
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To Do: Implement AXI4-Lite and full AXI4 protocols.
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To Do: Implement AXI4-Lite and full AXI4 protocols.
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Author(s):
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Author(s):
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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either version 2.1 of the License, or (at your option) any
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later version.
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later version.
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This source is distributed in the hope that it will be
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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details.
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You should have received a copy of the GNU Lesser General
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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from http://www.opencores.org/lgpl.shtml.
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*/
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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--library tauhop; use tauhop.axiTransactor.all;
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--library tauhop; use tauhop.axiTransactor.all;
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--/* TODO remove once generic packages are supported. */
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--/* TODO remove once generic packages are supported. */
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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entity axiBfmMaster is
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entity axiBfmMaster is
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port(aclk,n_areset:in std_ulogic;
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port(aclk,n_areset:in std_ulogic;
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/* BFM signalling. */
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/* BFM signalling. */
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readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false);
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readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false);
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readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
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readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
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/* AXI Master interface */
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/* AXI Master interface */
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axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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-- /* AXI Slave interface */
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-- /* AXI Slave interface */
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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symbolsPerTransfer:in t_cnt;
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symbolsPerTransfer:in t_cnt;
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outstandingTransactions:buffer t_cnt;
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outstandingTransactions:buffer t_cnt;
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/* Debug ports. */
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/* Debug ports. */
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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dbg_axiTxFsm:out axiBfmStatesTx:=idle
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dbg_axiTxFsm:out axiBfmStatesTx:=idle
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);
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);
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end entity axiBfmMaster;
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end entity axiBfmMaster;
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architecture rtl of axiBfmMaster is
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architecture rtl of axiBfmMaster is
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/* Finite-state Machines. */
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/* Finite-state Machines. */
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signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
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signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
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/* BFM signalling. */
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/* BFM signalling. */
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signal i_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_readResponse,i_writeResponse:t_bfm;
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signal i_readResponse,i_writeResponse:t_bfm;
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begin
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begin
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/* Transaction counter. */
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/* Transaction counter. */
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process(n_areset,symbolsPerTransfer,aclk) is begin
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process(n_areset,symbolsPerTransfer,aclk) is begin
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/* Using synchronous reset will meet timing. However, because outstandingTransactions is a huge
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--if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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register set, using asynchronous reset will violate timing.
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if falling_edge(aclk) then
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FIXME Try and close timing even with asynchronous reset applied on outstandingTransactions.
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/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
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Using asynchronous reset will help to lower power.
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*/
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if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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elsif falling_edge(aclk) then
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else
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if outstandingTransactions<1 then
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if outstandingTransactions<1 then
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outstandingTransactions<=symbolsPerTransfer;
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outstandingTransactions<=symbolsPerTransfer;
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report "No more pending transactions." severity note;
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report "No more pending transactions." severity note;
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elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
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elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_ns: process(all) is begin
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axi_bfmTx_ns: process(all) is begin
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axiTxState<=next_axiTxState;
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axiTxState<=next_axiTxState;
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if not n_areset then axiTxState<=idle;
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if not n_areset then axiTxState<=idle;
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else
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else
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case next_axiTxState is
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case next_axiTxState is
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when idle=>
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when idle=>
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if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
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if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
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when payload=>
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when payload=>
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if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
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if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
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when endOfTx=>
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when endOfTx=>
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axiTxState<=idle;
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axiTxState<=idle;
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when others=>axiTxState<=idle;
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when others=>axiTxState<=idle;
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end case;
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end case;
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end if;
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end if;
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end process axi_bfmTx_ns;
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end process axi_bfmTx_ns;
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/* output logic for AXI4-Stream Master Tx BFM. */
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/* output logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_op: process(all) is begin
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axi_bfmTx_op: process(all) is begin
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i_writeResponse<=writeResponse;
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i_writeResponse<=writeResponse;
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axiMaster_out.tValid<=false;
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axiMaster_out.tValid<=false;
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axiMaster_out.tLast<=false;
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axiMaster_out.tLast<=false;
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axiMaster_out.tData<=(others=>'Z');
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axiMaster_out.tData<=(others=>'Z');
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i_writeResponse.trigger<=false;
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i_writeResponse.trigger<=false;
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if writeRequest.trigger xor i_writeRequest.trigger then
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if writeRequest.trigger xor i_writeRequest.trigger then
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axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tValid<=true;
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axiMaster_out.tValid<=true;
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end if;
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end if;
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if not n_areset then axiMaster_out.tData<=(others=>'Z');
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else
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case next_axiTxState is
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case next_axiTxState is
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when payload=>
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when payload=>
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axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tValid<=true;
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axiMaster_out.tValid<=true;
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if axiMaster_in.tReady then
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if axiMaster_in.tReady then
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i_writeResponse.trigger<=true;
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i_writeResponse.trigger<=true;
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end if;
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end if;
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/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */
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/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */
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if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if;
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if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if;
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when others=> null;
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when others=> null;
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end case;
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end case;
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end if;
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end process axi_bfmTx_op;
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end process axi_bfmTx_op;
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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process(n_areset,aclk) is begin
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process(n_areset,aclk) is begin
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if falling_edge(aclk) then
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if falling_edge(aclk) then
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next_axiTxState<=axiTxState;
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next_axiTxState<=axiTxState;
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i_writeRequest<=writeRequest;
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i_writeRequest<=writeRequest;
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end if;
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end if;
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end process;
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end process;
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process(aclk) is begin
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process(aclk) is begin
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if rising_edge(aclk) then
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if rising_edge(aclk) then
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writeResponse<=i_writeResponse;
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writeResponse<=i_writeResponse;
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end if;
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end if;
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end process;
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end process;
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dbg_axiTxFSM<=axiTxState;
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dbg_axiTxFSM<=axiTxState;
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end architecture rtl;
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end architecture rtl;
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