/*
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/*
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This file is part of the AXI4 Transactor and Bus Functional Model
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This file is part of the AXI4 Transactor and Bus Functional Model
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(axi4_tlm_bfm) project:
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(axi4_tlm_bfm) project:
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http://www.opencores.org/project,axi4_tlm_bfm
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http://www.opencores.org/project,axi4_tlm_bfm
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Description
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Description
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Implementation of AXI4 Master BFM core according to AXI4 protocol
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Implementation of AXI4 Master BFM core according to AXI4 protocol
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specification document.
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specification document.
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To Do: Implement AXI4-Lite and full AXI4 protocols.
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To Do: Implement AXI4-Lite and full AXI4 protocols.
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Author(s):
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Author(s):
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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either version 2.1 of the License, or (at your option) any
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later version.
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later version.
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This source is distributed in the hope that it will be
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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details.
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You should have received a copy of the GNU Lesser General
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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from http://www.opencores.org/lgpl.shtml.
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*/
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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--library tauhop; use tauhop.axiTransactor.all;
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--library tauhop; use tauhop.axiTransactor.all;
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/* TODO remove once generic packages are supported. */
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/* TODO remove once generic packages are supported. */
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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library tauhop; use tauhop.fsm.all, tauhop.tlm.all, tauhop.axiTLM.all;
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entity axiBfmMaster is
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entity axiBfmMaster is
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port(aclk,n_areset:in std_ulogic;
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port(aclk,n_areset:in std_ulogic;
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/* BFM signalling. */
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/* BFM signalling. */
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readRequest,writeRequest:in t_bfm:=(address=>(others=>'X'), message=>(others=>'X'), trigger=>false);
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readRequest,writeRequest:in t_bfm:=(address=>(others=>'X'), message=>(others=>'X'), trigger=>false);
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readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
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readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
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/* AXI Master interface */
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/* AXI Master interface */
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axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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-- /* AXI Slave interface */
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-- /* AXI Slave interface */
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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lastTransaction:in boolean;
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lastTransaction:in boolean;
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/* Debug ports. */
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/* Debug ports. */
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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dbg_axiTxFsm:out axiBfmStatesTx:=idle
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dbg_axiTxFsm:out axiBfmStatesTx:=idle
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);
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);
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end entity axiBfmMaster;
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end entity axiBfmMaster;
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architecture rtl of axiBfmMaster is
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architecture rtl of axiBfmMaster is
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/* Finite-state Machines. */
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/* Finite-state Machines. */
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signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
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signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
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signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
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signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
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signal i_trigger,trigger:boolean;
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signal i_trigger,trigger:boolean;
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/* BFM signalling. */
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/* BFM signalling. */
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-- signal i_readRequest,i_writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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-- signal i_readRequest,i_writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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-- signal i_readResponse,i_writeResponse:t_bfm;
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-- signal i_readResponse,i_writeResponse:t_bfm;
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signal i_writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal i_writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal i_writeResponse:t_bfm;
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signal i_writeResponse:t_bfm;
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/* DDR Pipelines. */
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signal next_axiTxState_rise,next_axiTxState_fall:axiBfmStatesTx;
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signal i_writeRequest_rise,i_writeRequest_fall:t_bfm;
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signal writeResponse_rise,writeResponse_fall:t_bfm;
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signal axiMaster_out_rise,axiMaster_out_fall:t_axi4StreamTransactor_m2s;
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signal trigger_rise,trigger_fall:boolean;
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begin
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begin
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i_trigger<=writeRequest.trigger xor i_writeRequest.trigger;
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i_trigger<=writeRequest.trigger xor i_writeRequest.trigger;
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_ns: process(all) is begin
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axi_bfmTx_ns: process(all) is begin
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axiTxState<=next_axiTxState;
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axiTxState<=next_axiTxState;
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if not n_areset then axiTxState<=idle;
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if not n_areset then axiTxState<=idle;
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else
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else
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case next_axiTxState is
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case next_axiTxState is
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when idle=>
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when idle=>
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if i_trigger then axiTxState<=payload; end if;
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if i_trigger then axiTxState<=payload; end if;
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when payload=>
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when payload=>
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if lastTransaction then axiTxState<=endOfTx; end if;
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if lastTransaction then axiTxState<=endOfTx; end if;
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when endOfTx=>
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when endOfTx=>
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axiTxState<=idle;
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if axiMaster_in.tReady then axiTxState<=idle; end if;
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when others=>axiTxState<=idle;
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when others=>axiTxState<=idle;
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end case;
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end case;
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end if;
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end if;
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end process axi_bfmTx_ns;
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end process axi_bfmTx_ns;
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/* output logic for AXI4-Stream Master Tx BFM. */
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/* output logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_op: process(all) is begin
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axi_bfmTx_op: process(all) is begin
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i_writeResponse<=writeResponse;
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i_writeResponse<=writeResponse;
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i_axiMaster_out<=axiMaster_out;
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i_axiMaster_out<=axiMaster_out;
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i_axiMaster_out.tLast<=false;
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i_axiMaster_out.tLast<=false;
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i_writeResponse.trigger<=false;
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i_writeResponse.trigger<=false;
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case next_axiTxState is
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case next_axiTxState is
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when idle=>
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when idle=>
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i_axiMaster_out.tValid<=false;
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i_axiMaster_out.tValid<=false;
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i_axiMaster_out.tData<=(others=>'Z');
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i_axiMaster_out.tData<=(others=>'Z');
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if i_trigger then
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if i_trigger then
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i_axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tValid<=true;
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i_axiMaster_out.tValid<=true;
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end if;
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end if;
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when payload | endOfTx =>
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when payload | endOfTx =>
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if i_trigger then
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if i_trigger then
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i_axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tValid<=true;
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i_axiMaster_out.tValid<=true;
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end if;
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end if;
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if axiMaster_in.tReady then
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if axiMaster_in.tReady then
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i_writeResponse.trigger<=true;
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i_writeResponse.trigger<=true;
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end if;
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end if;
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if lastTransaction then i_axiMaster_out.tLast<=true; end if;
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if lastTransaction then i_axiMaster_out.tLast<=true; end if;
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when others=> null;
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when others=> null;
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end case;
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end case;
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end process axi_bfmTx_op;
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end process axi_bfmTx_op;
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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process(aclk) is begin
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process(aclk) is begin
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if falling_edge(aclk) then
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if not n_areset then
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next_axiTxState<=idle;
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i_writeRequest<=(address=>(others=>'0'),message=>(others=>'0'),trigger=>false);
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writeResponse<=(address=>(others=>'0'),message=>(others=>'0'),trigger=>false);
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--axiMaster_out<=(others=>'0');
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trigger<=false;
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-- elsif rising_edge(aclk) then
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-- next_axiTxState<=axiTxState;
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-- i_writeRequest<=writeRequest;
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-- writeResponse<=i_writeResponse;
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-- axiMaster_out<=i_axiMaster_out;
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-- trigger<=i_trigger;
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elsif falling_edge(aclk) then
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next_axiTxState<=axiTxState;
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next_axiTxState<=axiTxState;
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i_writeRequest<=writeRequest;
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i_writeRequest<=writeRequest;
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writeResponse<=i_writeResponse;
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writeResponse<=i_writeResponse;
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axiMaster_out<=i_axiMaster_out;
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axiMaster_out<=i_axiMaster_out;
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trigger<=i_trigger;
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trigger<=i_trigger;
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end if;
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end if;
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end process;
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end process;
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/*
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process(n_areset,aclk) is begin
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if not n_areset then
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next_axiTxState_rise<=idle;
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elsif rising_edge(aclk) then
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next_axiTxState_rise<=axiTxState;
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i_writeRequest_rise<=writeRequest;
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writeResponse_rise<=i_writeResponse;
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axiMaster_out_rise<=i_axiMaster_out;
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trigger_rise<=i_trigger;
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end if;
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end process;
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process(n_areset,aclk) is begin
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if not n_areset then
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next_axiTxState_fall<=idle;
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elsif falling_edge(aclk) then
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next_axiTxState_fall<=axiTxState;
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i_writeRequest_fall<=writeRequest;
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writeResponse_fall<=i_writeResponse;
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axiMaster_out_fall<=i_axiMaster_out;
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trigger_fall<=i_trigger;
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end if;
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end process;
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next_axiTxState<=idle when not n_areset else next_axiTxState_rise xor next_axiTxState_fall;
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*/
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-- pseudo dual-edge-triggered D-Flip-Flop (Refer Ralf Hildebrant's paper: http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf).
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/*
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process(async_clr,clk)
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begin
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if impl_rp=0 and async_clr='0' then ff_rise<='0';
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elsif impl_rp=1 and async_clr='0' then ff_rise<='1';
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elsif rising_edge(clk) then
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if d='1' then ff_rise<=not ff_fall;
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else ff_rise<=ff_fall;
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end if;
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end if;
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end process;
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process(async_clr,clk)
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begin
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if impl_rp=0 and async_clr='0' then ff_fall<='0';
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elsif impl_rp=1 and async_clr='0' then ff_fall<='1';
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elsif falling_edge(clk) then
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if d='1' then ff_fall<=not ff_rise;
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else ff_fall<=ff_rise;
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end if;
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end if;
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end process;
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q<='0' when impl_rp=0 and async_clr='0' else
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'1' when impl_rp=1 and async_clr='0' else
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ff_rise xor ff_fall;
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*/
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-- end pseudo dual-edge-triggered DFF
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/*
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-- process(n_areset,aclk) is
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process(aclk) is
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-- variable q1,q2:std_ulogic_vector(q'length-1 downto 0);
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variable q_a1,q_a2:axiBfmStatesTx; --std_ulogic_vector(axiTxState'range);
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variable q_b1,q_b2:t_bfm; --std_ulogic_vector(writeRequest'range);
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variable q_c1,q_c2:t_bfm;
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variable q_d1,q_d2:t_axi4StreamTransactor_m2s;
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variable q_e1,q_e2:boolean;
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begin
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-- if not n_areset then
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-- q_a1:=idle; q_a2:=idle;
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-- q_b1:=(others=>'0'); q_b2:=(others=>'0');
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-- q_c1:=(others=>'0'); q_c2:=(others=>'0');
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-- q_d1:=(others=>'0'); q_d2:=(others=>'0');
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-- q_e1:=(others=>'0'); q_e2:=(others=>'0');
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if rising_edge(aclk) then
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q_a1:=axiTxState xor q_a2;
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q_b1:=writeRequest xor q_b2;
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q_c1:=i_writeResponse xor q_c2;
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q_d1:=i_axiMaster_out xor q_d2;
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q_e1:=i_trigger xor q_e2;
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elsif falling_edge(aclk) then
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q_a2:=axiTxState xor q_a1;
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q_b2:=writeRequest xor q_b1;
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q_c2:=i_writeResponse xor q_c1;
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q_d2:=i_axiMaster_out xor q_d1;
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q_e2:=i_trigger xor q_e1;
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end if;
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next_axiTxState<=q_a1 xor q_a2;
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i_writeRequest<=q_b1 xor q_b2;
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writeResponse<=q_c1 xor q_c2;
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axiMaster_out<=q_d1 xor q_d2;
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trigger<=q_e1 xor q_e2;
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end process;
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*/
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dbg_axiTxFSM<=axiTxState;
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dbg_axiTxFSM<=axiTxState;
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end architecture rtl;
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end architecture rtl;
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