/*
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/*
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This file is part of the AXI4 Transactor and Bus Functional Model
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This file is part of the AXI4 Transactor and Bus Functional Model
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(axi4_tlm_bfm) project:
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(axi4_tlm_bfm) project:
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http://www.opencores.org/project,axi4_tlm_bfm
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http://www.opencores.org/project,axi4_tlm_bfm
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|
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Description
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Description
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Synthesisable use case for AXI4 on-chip messaging.
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Synthesisable use case for AXI4 on-chip messaging.
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To Do:
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To Do:
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Author(s):
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Author(s):
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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either version 2.1 of the License, or (at your option) any
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later version.
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later version.
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This source is distributed in the hope that it will be
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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details.
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You should have received a copy of the GNU Lesser General
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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from http://www.opencores.org/lgpl.shtml.
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*/
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
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--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
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/* TODO remove once generic packages are supported. */
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/* TODO remove once generic packages are supported. */
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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/* synthesis translate_off */
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/* synthesis translate_off */
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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/* synthesis translate_on */
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/* synthesis translate_on */
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library altera; use altera.stp;
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library altera; use altera.stp;
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entity user is port(
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entity user is port(
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/* Comment-out for simulation. */
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/* Comment-out for simulation. */
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clk,nReset:in std_ulogic;
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clk,nReset:in std_ulogic;
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/* AXI Master interface */
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/* AXI Master interface */
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-- axiMaster_in:in t_axi4StreamTransactor_s2m;
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-- axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s
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axiMaster_out:buffer t_axi4StreamTransactor_m2s
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/* Debug ports. */
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/* Debug ports. */
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);
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);
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end entity user;
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end entity user;
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architecture rtl of user is
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architecture rtl of user is
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/* Global counters. */
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/* Global counters. */
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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signal symbolsPerTransfer:t_cnt;
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signal symbolsPerTransfer:t_cnt;
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signal outstandingTransactions:t_cnt;
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signal outstandingTransactions:t_cnt;
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/* BFM signalling. */
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/* BFM signalling. */
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signal readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal readResponse:t_bfm;
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signal readResponse:t_bfm;
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signal writeResponse:t_bfm;
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signal writeResponse:t_bfm;
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type txStates is (idle,transmitting);
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type txStates is (idle,transmitting);
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signal txFSM,i_txFSM:txStates;
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signal txFSM,i_txFSM:txStates;
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/* Tester signals. */
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/* Tester signals. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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signal clk,reset:std_ulogic:='0';
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signal clk,reset:std_ulogic:='0';
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/* synthesis translate_on */
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/* synthesis translate_on */
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signal cnt:unsigned(3 downto 0);
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signal cnt:unsigned(3 downto 0);
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signal reset:std_ulogic:='0';
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signal reset:std_ulogic:='0';
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signal testerClk:std_ulogic;
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signal testerClk:std_ulogic;
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--signal trigger:boolean;
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--signal trigger:boolean;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal anlysr_dataIn:std_logic_vector(127 downto 0);
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signal anlysr_dataIn:std_logic_vector(127 downto 0);
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signal anlysr_trigger:std_ulogic;
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signal anlysr_trigger:std_ulogic;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal irq_write:std_ulogic; -- clock gating.
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signal irq_write:std_ulogic; -- clock gating.
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begin
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begin
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/* Bus functional models. */
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/* Bus functional models. */
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axiMaster: entity work.axiBfmMaster(rtl)
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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port map(
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port map(
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aclk=>irq_write, n_areset=>not reset,
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aclk=>irq_write, n_areset=>not reset,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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readResponse=>readResponse, writeResponse=>writeResponse,
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axiMaster_in=>axiMaster_in,
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axiMaster_in=>axiMaster_in,
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axiMaster_out=>axiMaster_out,
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axiMaster_out=>axiMaster_out,
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symbolsPerTransfer=>symbolsPerTransfer,
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symbolsPerTransfer=>symbolsPerTransfer,
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outstandingTransactions=>outstandingTransactions,
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outstandingTransactions=>outstandingTransactions,
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dbg_axiTxFSM=>dbg_axiTxFSM
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dbg_axiTxFSM=>dbg_axiTxFSM
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);
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);
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/* Interrupt-request generator. */
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/* Interrupt-request generator. */
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irq_write<=clk when not reset else '0';
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irq_write<=clk when not reset else '0';
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/* Simulation Tester. */
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/* Simulation Tester. */
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/* PLL to generate tester's clock. */
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/* PLL to generate tester's clock. */
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f100MHz: entity altera.pll(syn) port map(
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f100MHz: entity altera.pll(syn) port map(
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areset=>'0', --not reset, --not nReset,
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areset=>'0', --not nReset,
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inclk0=>clk,
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inclk0=>clk,
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c0=>testerClk,
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c0=>testerClk,
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locked=>open
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locked=>open
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);
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);
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/* synthesis translate_off */
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/* synthesis translate_off */
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clk<=not clk after 10 ps;
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clk<=not clk after 10 ps;
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process is begin
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process is begin
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nReset<='1'; wait for 1 ps;
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nReset<='1'; wait for 1 ps;
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nReset<='0'; wait for 500 ps;
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nReset<='0'; wait for 500 ps;
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nReset<='1';
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nReset<='1';
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wait;
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wait;
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end process;
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end process;
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/* synthesis translate_on */
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/* synthesis translate_on */
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/* Hardware tester. */
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/* Hardware tester. */
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por: process(nReset,clk) is
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por: process(nReset,clk) is
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--variable cnt:unsigned(7 downto 0):=(others=>'1');
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--variable cnt:unsigned(7 downto 0):=(others=>'1');
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begin
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begin
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if not nReset then cnt<=(others=>'1');
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if not nReset then cnt<=(others=>'1');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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reset<='0';
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reset<='0';
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if cnt>0 then reset<='1'; cnt<=cnt-1; end if;
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if cnt>0 then reset<='1'; cnt<=cnt-1; end if;
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end if;
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end if;
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end process por;
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end process por;
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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anlysr_trigger<='1' when writeRequest.trigger else '0';
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--anlysr_trigger<='1' when writeRequest.trigger else '0';
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--anlysr_trigger<='1' when reset else '0';
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anlysr_trigger<='1' when reset else '0';
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/* Disable this for synthesis as this is not currently synthesisable.
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/* Disable this for synthesis as this is not currently synthesisable.
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Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
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Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
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*/
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*/
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/* synthesis translate_off */
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/* synthesis translate_off */
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--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
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--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
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/* synthesis translate_on */
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/* synthesis translate_on */
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anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
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anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
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anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
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anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
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--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
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--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
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anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
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anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
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anlysr_dataIn(18)<='1' when clk else '0';
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anlysr_dataIn(18)<='1' when clk else '0';
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anlysr_dataIn(19)<='1' when reset else '0';
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anlysr_dataIn(19)<='1' when reset else '0';
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anlysr_dataIn(20)<='1' when irq_write else '0';
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anlysr_dataIn(20)<='1' when irq_write else '0';
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anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
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anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
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anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
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anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
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anlysr_dataIn(86 downto 23)<=std_logic_vector(axiMaster_out.tData);
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anlysr_dataIn(86 downto 23)<=std_logic_vector(axiMaster_out.tData);
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anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
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anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
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anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
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anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
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anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
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anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
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anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
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anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
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anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
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anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
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--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);
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--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);
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anlysr_dataIn(101 downto 98)<=std_logic_vector(cnt);
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anlysr_dataIn(101 downto 98)<=std_logic_vector(cnt);
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anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0');
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anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0');
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/* Simulate only if you have compiled Altera's simulation libraries. */
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/* Simulate only if you have compiled Altera's simulation libraries. */
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i_bistFramer_stp_analyser: entity altera.stp(syn) port map(
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i_bist_logicAnalyser: entity altera.stp(syn) port map(
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acq_clk=>testerClk,
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acq_clk=>testerClk,
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acq_data_in=>anlysr_dataIn,
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acq_data_in=>anlysr_dataIn,
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acq_trigger_in=>"1",
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acq_trigger_in=>"1",
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trigger_in=>anlysr_trigger
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trigger_in=>anlysr_trigger
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);
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);
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/* Stimuli sequencer. TODO move to tester/stimuli.
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/* Stimuli sequencer. TODO move to tester/stimuli.
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This emulates the AXI4-Stream Slave.
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This emulates the AXI4-Stream Slave.
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*/
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*/
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/* Simulation-only stimuli sequencer. */
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/* Simulation-only stimuli sequencer. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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process is begin
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process is begin
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/* Fast read. */
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/* Fast read. */
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while not axiMaster_out.tLast loop
|
while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
|
while not axiMaster_out.tValid loop
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
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end loop;
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end loop;
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|
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axiMaster_in.tReady<=true;
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axiMaster_in.tReady<=true;
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|
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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axiMaster_in.tReady<=false;
|
end loop;
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end loop;
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|
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
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|
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/* Normal read. */
|
/* Normal read. */
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while not axiMaster_out.tLast loop
|
while not axiMaster_out.tLast loop
|
/* Wait for tValid to assert. */
|
/* Wait for tValid to assert. */
|
while not axiMaster_out.tValid loop
|
while not axiMaster_out.tValid loop
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
end loop;
|
end loop;
|
|
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
axiMaster_in.tReady<=true;
|
axiMaster_in.tReady<=true;
|
|
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
|
axiMaster_in.tReady<=false;
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end loop;
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end loop;
|
|
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for i in 0 to 10 loop
|
for i in 0 to 10 loop
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wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
end loop;
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end loop;
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|
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/* One-shot read. */
|
/* One-shot read. */
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axiMaster_in.tReady<=true;
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axiMaster_in.tReady<=true;
|
|
|
wait until falling_edge(clk);
|
wait until falling_edge(clk);
|
axiMaster_in.tReady<=false;
|
axiMaster_in.tReady<=false;
|
|
|
wait;
|
wait;
|
end process;
|
end process;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
/* Synthesisable stimuli sequencer. */
|
/* Synthesisable stimuli sequencer. */
|
process(clk) is begin
|
process(clk) is begin
|
if falling_edge(clk) then
|
if falling_edge(clk) then
|
axiMaster_in.tReady<=false;
|
axiMaster_in.tReady<=false;
|
--if axiMaster_out.tValid and not axiMaster_out.tLast then
|
--if axiMaster_out.tValid and not axiMaster_out.tLast then
|
if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
|
if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
|
axiMaster_in.tReady<=true;
|
axiMaster_in.tReady<=true;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
/* Data transmitter. */
|
/* Data transmitter. */
|
sequencer_ns: process(all) is begin
|
sequencer_ns: process(all) is begin
|
txFSM<=i_txFSM;
|
txFSM<=i_txFSM;
|
if reset then txFSM<=idle;
|
if reset then txFSM<=idle;
|
else
|
else
|
case i_txFSM is
|
case i_txFSM is
|
when idle=>
|
when idle=>
|
if outstandingTransactions>0 then txFSM<=transmitting; end if;
|
if outstandingTransactions>0 then txFSM<=transmitting; end if;
|
when transmitting=>
|
when transmitting=>
|
if axiMaster_out.tLast then
|
if axiMaster_out.tLast then
|
txFSM<=idle;
|
txFSM<=idle;
|
end if;
|
end if;
|
when others=> null;
|
when others=> null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process sequencer_ns;
|
end process sequencer_ns;
|
|
|
/* Data transmitter. */
|
/* Data transmitter. */
|
sequencer_op: process(reset,irq_write) is
|
sequencer_op: process(reset,irq_write) is
|
/* Local procedures to map BFM signals with the package procedure. */
|
/* Local procedures to map BFM signals with the package procedure. */
|
procedure read(address:in t_addr) is begin
|
procedure read(address:in t_addr) is begin
|
read(readRequest,address);
|
read(readRequest,address);
|
end procedure read;
|
end procedure read;
|
|
|
procedure write(data:in t_msg) is begin
|
procedure write(data:in t_msg) is begin
|
write(request=>writeRequest, address=>(others=>'-'), data=>data);
|
write(request=>writeRequest, address=>(others=>'-'), data=>data);
|
end procedure write;
|
end procedure write;
|
|
|
variable isPktError:boolean;
|
variable isPktError:boolean;
|
|
|
/* Tester variables. */
|
/* Tester variables. */
|
/* Synthesis-only randomisation. */
|
/* Synthesis-only randomisation. */
|
variable rand0:signed(63 downto 0);
|
variable rand0:signed(63 downto 0);
|
/* Simulation-only randomisation. */
|
/* Simulation-only randomisation. */
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
variable rv0:RandomPType;
|
variable rv0:RandomPType;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
begin
|
begin
|
if reset then
|
if reset then
|
/* synthesis only. */
|
/* synthesis only. */
|
rand0:=(others=>'0');
|
rand0:=(others=>'0');
|
|
|
/* simulation only. */
|
/* simulation only. */
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
rv0.InitSeed(rv0'instance_name);
|
rv0.InitSeed(rv0'instance_name);
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
--txFSM<=idle;
|
--txFSM<=idle;
|
elsif falling_edge(irq_write) then
|
elsif falling_edge(irq_write) then
|
case txFSM is
|
case txFSM is
|
when transmitting=>
|
when transmitting=>
|
if txFSM/=i_txFSM or writeResponse.trigger then
|
if txFSM/=i_txFSM or writeResponse.trigger then
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
write(rv0.RandSigned(axiMaster_out.tData'length));
|
write(rv0.RandSigned(axiMaster_out.tData'length));
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
write(rand0);
|
write(rand0);
|
rand0:=rand0+1;
|
rand0:=rand0+1;
|
end if;
|
end if;
|
when others=>null;
|
when others=>null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process sequencer_op;
|
end process sequencer_op;
|
|
|
sequencer_regs: process(irq_write) is begin
|
sequencer_regs: process(irq_write) is begin
|
if falling_edge(irq_write) then
|
if falling_edge(irq_write) then
|
i_txFSM<=txFSM;
|
i_txFSM<=txFSM;
|
end if;
|
end if;
|
end process sequencer_regs;
|
end process sequencer_regs;
|
|
|
|
|
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
|
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
|
process(reset,irq_write) is
|
process(reset,irq_write) is
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
variable rv0:RandomPType;
|
variable rv0:RandomPType;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
begin
|
begin
|
if reset then
|
if reset then
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
rv0.InitSeed(rv0'instance_name);
|
rv0.InitSeed(rv0'instance_name);
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
symbolsPerTransfer<=128x"8";
|
symbolsPerTransfer<=128x"8";
|
elsif rising_edge(irq_write) then
|
elsif rising_edge(irq_write) then
|
if axiMaster_out.tLast then
|
if axiMaster_out.tLast then
|
/* synthesis only. */
|
/* synthesis only. */
|
/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
|
/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
|
--symbolsPerTransfer<=(others=>'0');
|
--symbolsPerTransfer<=(others=>'0');
|
|
|
/* Testcase 2: number of symbols per transfer is randomised. */
|
/* Testcase 2: number of symbols per transfer is randomised. */
|
--uniform(seed0,seed1,rand0);
|
--uniform(seed0,seed1,rand0);
|
--symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
|
--symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
|
--report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
|
--report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
|
|
|
|
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff";
|
symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff";
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
end architecture rtl;
|
end architecture rtl;
|
|
|
