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<##//////////////////////////////////////////////////////////////////
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////  Author: Eyal Hochberg                                      ////
////  Author: Eyal Hochberg                                      ////
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OUTFILE PREFIX_ic_decerr.v
OUTFILE PREFIX_ic_decerr.v
 
 
module PREFIX_ic_decerr(PORTS);
module PREFIX_ic_decerr(PORTS);
 
 
   input                          clk;
   input                          clk;
   input                          reset;
   input                          reset;
 
 
   input                          AWIDOK;
   input                          AWIDOK;
   input                          ARIDOK;
   input                          ARIDOK;
   port                           GROUP_IC_AXI;
   port                           GROUP_IC_AXI;
 
 
 
 
   parameter                      RESP_SLVERR = 2'b10;
   parameter                      RESP_SLVERR = 2'b10;
   parameter                      RESP_DECERR = 2'b11;
   parameter                      RESP_DECERR = 2'b11;
 
 
 
 
   reg                            AWREADY;
   reg                            AWREADY;
   reg [ID_BITS-1:0]               BID;
   reg [ID_BITS-1:0]               BID;
   reg [1:0]                       BRESP;
   reg [1:0]                       BRESP;
   reg                            BVALID;
   reg                            BVALID;
   reg                            ARREADY;
   reg                            ARREADY;
   reg [ID_BITS-1:0]               RID;
   reg [ID_BITS-1:0]               RID;
   reg [1:0]                       RRESP;
   reg [1:0]                       RRESP;
   reg                            RVALID;
   reg                            RVALID;
   reg [4-1:0]             rvalid_cnt;
   reg [4-1:0]                    rvalid_cnt;
 
 
 
 
 
IFDEF TRUE (USER_BITS>0)
   assign                         BUSER = 'd0;
   assign                         BUSER = 'd0;
   assign                         RUSER = 'd0;
   assign                         RUSER = 'd0;
 
ENDIF TRUE (USER_BITS>0)
 
 
   assign                         RDATA = {DATA_BITS{1'b0}};
   assign                         RDATA = {DATA_BITS{1'b0}};
 
 
 
 
   //WRITE
   //WRITE
   assign                         WREADY = 1'b1;
   assign                         WREADY = 1'b1;
 
 
   always @(posedge clk or posedge reset)
   always @(posedge clk or posedge reset)
     if (reset)
     if (reset)
       begin
       begin
          AWREADY <= #FFD 1'b1;
          AWREADY <= #FFD 1'b1;
          BID     <= #FFD {ID_BITS{1'b0}};
          BID     <= #FFD {ID_BITS{1'b0}};
          BRESP   <= #FFD 2'b00;
          BRESP   <= #FFD 2'b00;
       end
       end
     else if (BVALID & BREADY)
     else if (BVALID & BREADY)
       begin
       begin
          AWREADY <= #FFD 1'b1;
          AWREADY <= #FFD 1'b1;
       end
       end
     else if (AWVALID & AWREADY)
     else if (AWVALID & AWREADY)
       begin
       begin
          AWREADY <= #FFD 1'b0;
          AWREADY <= #FFD 1'b0;
          BID     <= #FFD AWID;
          BID     <= #FFD AWID;
          BRESP   <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;
          BRESP   <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;
       end
       end
 
 
   always @(posedge clk or posedge reset)
   always @(posedge clk or posedge reset)
     if (reset)
     if (reset)
       BVALID <= #FFD 1'b0;
       BVALID <= #FFD 1'b0;
     else if (WVALID & WREADY & WLAST)
     else if (WVALID & WREADY & WLAST)
       BVALID <= #FFD 1'b1;
       BVALID <= #FFD 1'b1;
     else if (BVALID & BREADY)
     else if (BVALID & BREADY)
       BVALID <= #FFD 1'b0;
       BVALID <= #FFD 1'b0;
 
 
 
 
   //READ   
   //READ   
   always @(posedge clk or posedge reset)
   always @(posedge clk or posedge reset)
     if (reset)
     if (reset)
       begin
       begin
          ARREADY <= #FFD 1'b1;
          ARREADY <= #FFD 1'b1;
          RID     <= #FFD {ID_BITS{1'b0}};
          RID     <= #FFD {ID_BITS{1'b0}};
          RRESP   <= #FFD 2'b00;
          RRESP   <= #FFD 2'b00;
       end
       end
     else if (RVALID & RREADY & RLAST)
     else if (RVALID & RREADY & RLAST)
       begin
       begin
          ARREADY <= #FFD 1'b1;
          ARREADY <= #FFD 1'b1;
       end
       end
     else if (ARVALID & ARREADY)
     else if (ARVALID & ARREADY)
       begin
       begin
          ARREADY <= #FFD 1'b0;
          ARREADY <= #FFD 1'b0;
          RID     <= #FFD ARID;
          RID     <= #FFD ARID;
          RRESP   <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;
          RRESP   <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;
       end
       end
 
 
 
 
   always @(posedge clk or posedge reset)
   always @(posedge clk or posedge reset)
     if (reset)
     if (reset)
       rvalid_cnt <= #FFD {4{1'b0}};
       rvalid_cnt <= #FFD {4{1'b0}};
     else if (RVALID & RREADY & RLAST)
     else if (RVALID & RREADY & RLAST)
       rvalid_cnt <= #FFD {4{1'b0}};
       rvalid_cnt <= #FFD {4{1'b0}};
     else if (RVALID & RREADY)
     else if (RVALID & RREADY)
       rvalid_cnt <= #FFD rvalid_cnt - 1'b1;
       rvalid_cnt <= #FFD rvalid_cnt - 1'b1;
     else if (ARVALID & ARREADY)
     else if (ARVALID & ARREADY)
       rvalid_cnt <= #FFD ARLEN;
       rvalid_cnt <= #FFD ARLEN;
 
 
 
 
   always @(posedge clk or posedge reset)
   always @(posedge clk or posedge reset)
     if (reset)
     if (reset)
       RVALID <= #FFD 1'b0;
       RVALID <= #FFD 1'b0;
     else if (RVALID & RREADY & RLAST)
     else if (RVALID & RREADY & RLAST)
       RVALID <= #FFD 1'b0;
       RVALID <= #FFD 1'b0;
     else if (ARVALID & ARREADY)
     else if (ARVALID & ARREADY)
       RVALID <= #FFD 1'b1;
       RVALID <= #FFD 1'b1;
 
 
   assign RLAST = (rvalid_cnt == 'd0) & RVALID;
   assign RLAST = (rvalid_cnt == 'd0) & RVALID;
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
endmodule
 
 
 
 
 
 

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