<##//////////////////////////////////////////////////////////////////
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<##//////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////##>
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//////////////////////////////////////////////////////////////////##>
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OUTFILE PREFIX_ic_decerr.v
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OUTFILE PREFIX_ic_decerr.v
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module PREFIX_ic_decerr(PORTS);
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module PREFIX_ic_decerr(PORTS);
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input clk;
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input clk;
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input reset;
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input reset;
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input AWIDOK;
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input AWIDOK;
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input ARIDOK;
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input ARIDOK;
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port GROUP_IC_AXI;
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port GROUP_IC_AXI;
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parameter RESP_SLVERR = 2'b10;
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parameter RESP_SLVERR = 2'b10;
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parameter RESP_DECERR = 2'b11;
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parameter RESP_DECERR = 2'b11;
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reg AWREADY;
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reg AWREADY;
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reg [ID_BITS-1:0] BID;
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reg [ID_BITS-1:0] BID;
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reg [1:0] BRESP;
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reg [1:0] BRESP;
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reg BVALID;
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reg BVALID;
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reg ARREADY;
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reg ARREADY;
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reg [ID_BITS-1:0] RID;
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reg [ID_BITS-1:0] RID;
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reg [1:0] RRESP;
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reg [1:0] RRESP;
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reg RVALID;
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reg RVALID;
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reg [4-1:0] rvalid_cnt;
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reg [4-1:0] rvalid_cnt;
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IFDEF TRUE (USER_BITS>0)
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assign BUSER = 'd0;
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assign BUSER = 'd0;
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assign RUSER = 'd0;
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assign RUSER = 'd0;
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ENDIF TRUE (USER_BITS>0)
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assign RDATA = {DATA_BITS{1'b0}};
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assign RDATA = {DATA_BITS{1'b0}};
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//WRITE
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//WRITE
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assign WREADY = 1'b1;
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assign WREADY = 1'b1;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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AWREADY <= #FFD 1'b1;
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AWREADY <= #FFD 1'b1;
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BID <= #FFD {ID_BITS{1'b0}};
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BID <= #FFD {ID_BITS{1'b0}};
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BRESP <= #FFD 2'b00;
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BRESP <= #FFD 2'b00;
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end
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end
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else if (BVALID & BREADY)
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else if (BVALID & BREADY)
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begin
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begin
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AWREADY <= #FFD 1'b1;
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AWREADY <= #FFD 1'b1;
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end
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end
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else if (AWVALID & AWREADY)
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else if (AWVALID & AWREADY)
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begin
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begin
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AWREADY <= #FFD 1'b0;
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AWREADY <= #FFD 1'b0;
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BID <= #FFD AWID;
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BID <= #FFD AWID;
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BRESP <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;
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BRESP <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;
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end
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end
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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BVALID <= #FFD 1'b0;
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BVALID <= #FFD 1'b0;
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else if (WVALID & WREADY & WLAST)
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else if (WVALID & WREADY & WLAST)
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BVALID <= #FFD 1'b1;
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BVALID <= #FFD 1'b1;
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else if (BVALID & BREADY)
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else if (BVALID & BREADY)
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BVALID <= #FFD 1'b0;
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BVALID <= #FFD 1'b0;
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//READ
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//READ
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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ARREADY <= #FFD 1'b1;
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ARREADY <= #FFD 1'b1;
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RID <= #FFD {ID_BITS{1'b0}};
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RID <= #FFD {ID_BITS{1'b0}};
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RRESP <= #FFD 2'b00;
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RRESP <= #FFD 2'b00;
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end
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end
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else if (RVALID & RREADY & RLAST)
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else if (RVALID & RREADY & RLAST)
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begin
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begin
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ARREADY <= #FFD 1'b1;
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ARREADY <= #FFD 1'b1;
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end
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end
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else if (ARVALID & ARREADY)
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else if (ARVALID & ARREADY)
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begin
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begin
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ARREADY <= #FFD 1'b0;
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ARREADY <= #FFD 1'b0;
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RID <= #FFD ARID;
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RID <= #FFD ARID;
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RRESP <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;
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RRESP <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;
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end
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end
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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rvalid_cnt <= #FFD {4{1'b0}};
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rvalid_cnt <= #FFD {4{1'b0}};
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else if (RVALID & RREADY & RLAST)
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else if (RVALID & RREADY & RLAST)
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rvalid_cnt <= #FFD {4{1'b0}};
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rvalid_cnt <= #FFD {4{1'b0}};
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else if (RVALID & RREADY)
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else if (RVALID & RREADY)
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rvalid_cnt <= #FFD rvalid_cnt - 1'b1;
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rvalid_cnt <= #FFD rvalid_cnt - 1'b1;
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else if (ARVALID & ARREADY)
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else if (ARVALID & ARREADY)
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rvalid_cnt <= #FFD ARLEN;
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rvalid_cnt <= #FFD ARLEN;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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RVALID <= #FFD 1'b0;
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RVALID <= #FFD 1'b0;
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else if (RVALID & RREADY & RLAST)
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else if (RVALID & RREADY & RLAST)
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RVALID <= #FFD 1'b0;
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RVALID <= #FFD 1'b0;
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else if (ARVALID & ARREADY)
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else if (ARVALID & ARREADY)
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RVALID <= #FFD 1'b1;
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RVALID <= #FFD 1'b1;
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assign RLAST = (rvalid_cnt == 'd0) & RVALID;
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assign RLAST = (rvalid_cnt == 'd0) & RVALID;
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endmodule
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endmodule
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