/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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OUTFILE PREFIX_cmd_fifo.v
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OUTFILE PREFIX_cmd_fifo.v
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INCLUDE def_axi_slave.txt
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INCLUDE def_axi_slave.txt
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module PREFIX_cmd_fifo (PORTS);
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module PREFIX_cmd_fifo (PORTS);
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parameter DEPTH = 8;
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parameter DEPTH = 8;
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parameter DEPTH_BITS =
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parameter DEPTH_BITS =
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(DEPTH <= 2) ? 1 :
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(DEPTH <= 2) ? 1 :
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(DEPTH <= 4) ? 2 :
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(DEPTH <= 4) ? 2 :
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(DEPTH <= 8) ? 3 :
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(DEPTH <= 8) ? 3 :
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(DEPTH <= 16) ? 4 :
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(DEPTH <= 16) ? 4 :
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(DEPTH <= 32) ? 5 :
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(DEPTH <= 32) ? 5 :
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(DEPTH <= 64) ? 6 :
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(DEPTH <= 64) ? 6 :
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(DEPTH <= 128) ? 7 :
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(DEPTH <= 128) ? 7 :
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(DEPTH <= 256) ? 8 :
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(DEPTH <= 256) ? 8 :
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(DEPTH <= 512) ? 9 : 0; //0 is ilegal
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(DEPTH <= 512) ? 9 : 0; //0 is ilegal
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input clk;
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input clk;
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input reset;
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input reset;
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input [ADDR_BITS-1:0] AADDR;
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input [ADDR_BITS-1:0] AADDR;
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input [ID_BITS-1:0] AID;
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input [ID_BITS-1:0] AID;
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input [1:0] ASIZE;
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input [1:0] ASIZE;
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input [LEN_BITS-1:0] ALEN;
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input [LEN_BITS-1:0] ALEN;
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input AVALID;
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input AVALID;
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input AREADY;
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input AREADY;
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input VALID;
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input VALID;
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input READY;
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input READY;
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input LAST;
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input LAST;
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output [ADDR_BITS-1:0] cmd_addr;
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output [ADDR_BITS-1:0] cmd_addr;
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output [ID_BITS-1:0] cmd_id;
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output [ID_BITS-1:0] cmd_id;
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output [1:0] cmd_size;
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output [SIZE_BITS-1:0] cmd_size;
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output [LEN_BITS-1:0] cmd_len;
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output [LEN_BITS-1:0] cmd_len;
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output [1:0] cmd_resp;
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output [1:0] cmd_resp;
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output cmd_timeout;
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output cmd_timeout;
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output cmd_ready;
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output cmd_ready;
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output cmd_empty;
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output cmd_empty;
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output cmd_full;
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output cmd_full;
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wire push;
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wire push;
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wire pop;
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wire pop;
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wire empty;
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wire empty;
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wire full;
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wire full;
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wire [DEPTH_BITS:0] fullness;
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wire [DEPTH_BITS:0] fullness;
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wire [1:0] resp_in;
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wire [1:0] resp_in;
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wire timeout_in;
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wire timeout_in;
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wire timeout_out;
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wire timeout_out;
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reg [ADDR_BITS-1:0] SLVERR_addr = {ADDR_BITS{1'b1}};
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reg [ADDR_BITS-1:0] SLVERR_addr = {ADDR_BITS{1'b1}};
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reg [ADDR_BITS-1:0] DECERR_addr = {ADDR_BITS{1'b1}};
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reg [ADDR_BITS-1:0] DECERR_addr = {ADDR_BITS{1'b1}};
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reg [ADDR_BITS-1:0] TIMEOUT_addr = {ADDR_BITS{1'b1}};
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reg [ADDR_BITS-1:0] TIMEOUT_addr = {ADDR_BITS{1'b1}};
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parameter RESP_SLVERR = 2'b10;
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parameter RESP_SLVERR = 2'b10;
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parameter RESP_DECERR = 2'b11;
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parameter RESP_DECERR = 2'b11;
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assign resp_in =
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assign resp_in =
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push & (SLVERR_addr == AADDR) ? RESP_SLVERR :
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push & (SLVERR_addr == AADDR) ? RESP_SLVERR :
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push & (DECERR_addr == AADDR) ? RESP_DECERR : 2'b00;
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push & (DECERR_addr == AADDR) ? RESP_DECERR : 2'b00;
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assign timeout_in = push & (TIMEOUT_addr == AADDR);
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assign timeout_in = push & (TIMEOUT_addr == AADDR);
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assign cmd_timeout = timeout_out & (TIMEOUT_addr != 0);
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assign cmd_timeout = timeout_out & (TIMEOUT_addr != 0);
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assign cmd_full = full | (DEPTH == fullness);
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assign cmd_full = full | (DEPTH == fullness);
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assign cmd_empty = empty;
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assign cmd_empty = empty;
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assign cmd_ready = ~empty;
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assign cmd_ready = ~empty;
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assign push = AVALID & AREADY;
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assign push = AVALID & AREADY;
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assign pop = VALID & READY & LAST;
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assign pop = VALID & READY & LAST;
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CREATE prgen_fifo.v DEFCMD(DEFINE STUB)
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CREATE prgen_fifo.v DEFCMD(DEFINE STUB)
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prgen_fifo_stub #(ADDR_BITS+ID_BITS+LEN_BITS+2+2+1, DEPTH)
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prgen_fifo_stub #(ADDR_BITS+ID_BITS+SIZE_BITS+LEN_BITS+2+1, DEPTH)
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cmd_fifo(
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cmd_fifo(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.push(push),
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.push(push),
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.pop(pop),
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.pop(pop),
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.din({AADDR,
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.din({AADDR,
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AID,
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AID,
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ASIZE,
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ASIZE,
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ALEN,
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ALEN,
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resp_in,
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resp_in,
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timeout_in
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timeout_in
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}
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}
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),
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),
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.dout({cmd_addr,
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.dout({cmd_addr,
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cmd_id,
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cmd_id,
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cmd_size,
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cmd_size,
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cmd_len,
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cmd_len,
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cmd_resp,
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cmd_resp,
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timeout_out
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timeout_out
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}
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}
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),
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),
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.fullness(fullness),
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.fullness(fullness),
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.empty(empty),
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.empty(empty),
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.full(full)
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.full(full)
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);
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);
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endmodule
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endmodule
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