/////////////////////////////////////////////////////////////////////
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<##//////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////##>
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OUTFILE PREFIX_rd_buff.v
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OUTFILE PREFIX_rd_buff.v
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INCLUDE def_axi_slave.txt
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INCLUDE def_axi_slave.txt
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module PREFIX_rd_buff(PORTS);
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module PREFIX_rd_buff(PORTS);
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input clk;
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input clk;
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input reset;
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input reset;
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output RD;
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output RD;
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input [DATA_BITS-1:0] DOUT;
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input [DATA_BITS-1:0] DOUT;
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input [LEN_BITS-1:0] rcmd_len;
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input [LEN_BITS-1:0] rcmd_len;
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input [LEN_BITS-1:0] rcmd_len2;
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input [LEN_BITS-1:0] rcmd_len2;
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input [1:0] rcmd_resp;
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input [1:0] rcmd_resp;
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input rcmd_timeout;
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input rcmd_timeout;
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input rcmd_ready;
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input rcmd_ready;
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output RVALID;
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output RVALID;
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input RREADY;
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input RREADY;
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output RLAST;
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output RLAST;
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output [DATA_BITS-1:0] RDATA;
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output [DATA_BITS-1:0] RDATA;
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output [1:0] RRESP;
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output [1:0] RRESP;
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output RD_last;
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output RD_last;
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input RBUSY;
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input RBUSY;
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reg [LEN_BITS:0] valid_counter;
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reg [LEN_BITS:0] valid_counter;
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reg [LEN_BITS-1:0] rd_counter;
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reg [LEN_BITS-1:0] rd_counter;
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wire cmd_pending;
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wire cmd_pending;
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reg RVALID;
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reg RVALID;
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reg [1:0] RRESP;
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reg [1:0] RRESP;
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wire last_rd;
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wire last_rd;
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assign cmd_pending = RVALID & (~RREADY);
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assign cmd_pending = RVALID & (~RREADY);
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assign RDATA = DOUT;
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assign RDATA = DOUT;
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assign RD = rcmd_ready & (~cmd_pending) & (~RBUSY) & (~rcmd_timeout);
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assign RD = rcmd_ready & (~cmd_pending) & (~RBUSY) & (~rcmd_timeout);
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assign RD_last = RD & (rd_counter == rcmd_len);
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assign RD_last = RD & (rd_counter == rcmd_len);
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assign RLAST = RVALID & (valid_counter == rcmd_len2 + 1'b1);
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assign RLAST = RVALID & (valid_counter == rcmd_len2 + 1'b1);
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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RRESP <= #FFD 2'b00;
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RRESP <= #FFD 2'b00;
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else if (RD)
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else if (RD)
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RRESP <= #FFD rcmd_resp;
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RRESP <= #FFD rcmd_resp;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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RVALID <= #FFD 1'b0;
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RVALID <= #FFD 1'b0;
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else if (RD)
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else if (RD)
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RVALID <= #FFD 1'b1;
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RVALID <= #FFD 1'b1;
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else if (RVALID & RREADY)
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else if (RVALID & RREADY)
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RVALID <= #FFD 1'b0;
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RVALID <= #FFD 1'b0;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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valid_counter <= #FFD {LEN_BITS+1{1'b0}};
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valid_counter <= #FFD {LEN_BITS+1{1'b0}};
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else if (RVALID & RREADY & RLAST & RD)
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else if (RVALID & RREADY & RLAST & RD)
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valid_counter <= #FFD 'd1;
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valid_counter <= #FFD 'd1;
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else if (RVALID & RREADY & RLAST)
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else if (RVALID & RREADY & RLAST)
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valid_counter <= #FFD {LEN_BITS+1{1'b0}};
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valid_counter <= #FFD {LEN_BITS+1{1'b0}};
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else if (RD)
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else if (RD)
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valid_counter <= #FFD valid_counter + 1'b1;
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valid_counter <= #FFD valid_counter + 1'b1;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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rd_counter <= #FFD {LEN_BITS{1'b0}};
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rd_counter <= #FFD {LEN_BITS{1'b0}};
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else if (RD_last)
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else if (RD_last)
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rd_counter <= #FFD {LEN_BITS{1'b0}};
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rd_counter <= #FFD {LEN_BITS{1'b0}};
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else if (RD)
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else if (RD)
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rd_counter <= #FFD rd_counter + 1'b1;
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rd_counter <= #FFD rd_counter + 1'b1;
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endmodule
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endmodule
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