# biRISC-V - 32-bit dual issue RISC-V CPU
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# biRISC-V - 32-bit dual issue RISC-V CPU
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Github: [http://github.com/ultraembedded/biriscv](http://github.com/ultraembedded/biriscv)
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Github: [http://github.com/ultraembedded/biriscv](http://github.com/ultraembedded/biriscv)
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## Features
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## Features
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* 32-bit RISC-V ISA CPU core.
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* 32-bit RISC-V ISA CPU core.
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* Superscalar (dual-issue) in-order 6 or 7 stage pipeline.
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* Superscalar (dual-issue) in-order 6 or 7 stage pipeline.
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* Support RISC-V’s integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).
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* Support RISC-V’s integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).
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* Branch prediction (bimodel/gshare) with configurable depth branch target buffer (BTB) and return address stack (RAS).
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* Branch prediction (bimodel/gshare) with configurable depth branch target buffer (BTB) and return address stack (RAS).
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* 64-bit instruction fetch, 32-bit data access.
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* 64-bit instruction fetch, 32-bit data access.
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* 2 x integer ALU (arithmetic, shifters and branch units).
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* 2 x integer ALU (arithmetic, shifters and branch units).
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* 1 x load store unit, 1 x out-of-pipeline divider.
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* 1 x load store unit, 1 x out-of-pipeline divider.
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* Issue and complete up to 2 independent instructions per cycle.
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* Issue and complete up to 2 independent instructions per cycle.
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* Supports user, supervisor and machine mode privilege levels.
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* Supports user, supervisor and machine mode privilege levels.
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* Basic MMU support - capable of booting Linux with atomics (RV-A) SW emulation.
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* Basic MMU support - capable of booting Linux with atomics (RV-A) SW emulation.
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* Implements base ISA spec [v2.1](docs/riscv_isa_spec.pdf) and privileged ISA spec [v1.11](docs/riscv_privileged_spec.pdf).
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* Implements base ISA spec [v2.1](docs/riscv_isa_spec.pdf) and privileged ISA spec [v1.11](docs/riscv_privileged_spec.pdf).
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* Verified using [Google's RISCV-DV](https://github.com/google/riscv-dv) random instruction sequences using cosimulation against [C++ ISA model](https://github.com/ultraembedded/exactstep).
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* Verified using [Google's RISCV-DV](https://github.com/google/riscv-dv) random instruction sequences using cosimulation against [C++ ISA model](https://github.com/ultraembedded/exactstep).
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* Support for instruction / data cache, AXI bus interfaces or tightly coupled memories.
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* Support for instruction / data cache, AXI bus interfaces or tightly coupled memories.
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* Configurable number of pipeline stages, result forwarding options, and branch prediction resources.
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* Configurable number of pipeline stages, result forwarding options, and branch prediction resources.
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* Synthesizable Verilog 2001, Verilator and FPGA friendly.
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* Synthesizable Verilog 2001, Verilator and FPGA friendly.
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* Coremark: **4.1 CoreMark/MHz**
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* Coremark: **4.1 CoreMark/MHz**
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* Dhrystone: **1.9 DMIPS/MHz** ('legal compile options' / 337 instructions per iteration)
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* Dhrystone: **1.9 DMIPS/MHz** ('legal compile options' / 337 instructions per iteration)
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*A sequence showing execution of 2 instructions per cycle;*
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*A sequence showing execution of 2 instructions per cycle;*
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## Documentation
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## Documentation
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* [Configuration](http://github.com/ultraembedded/biriscv/docs/configuration.md)
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* [Configuration](https://github.com/ultraembedded/biriscv/blob/master/docs/configuration.md)
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* [Booting Linux](http://github.com/ultraembedded/biriscv/docs/linux.md)
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* [Booting Linux](https://github.com/ultraembedded/biriscv/blob/master/docs/linux.md)
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* [Integration](http://github.com/ultraembedded/biriscv/docs/integration.md)
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* [Integration](https://github.com/ultraembedded/biriscv/blob/master/docs/integration.md)
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* [Custom Features](http://github.com/ultraembedded/biriscv/docs/custom.md)
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* [Custom Features](https://github.com/ultraembedded/biriscv/blob/master/docs/custom.md)
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## Similar Cores
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## Similar Cores
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* [SiFive E76](https://www.sifive.com/cores/e76)
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* [SiFive E76](https://www.sifive.com/cores/e76)
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* RV32IMAFC
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* RV32IMAFC
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* Dual issue in-order 8 stage pipeline
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* Dual issue in-order 8 stage pipeline
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* 4 ALU units (2 early, 2 late)
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* 4 ALU units (2 early, 2 late)
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* :heavy_multiplication_x: *Commercial closed source core/$$*
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* :heavy_multiplication_x: *Commercial closed source core/$$*
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* [WD SweRV RISC-V Core EH1](https://github.com/chipsalliance/Cores-SweRV)
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* [WD SweRV RISC-V Core EH1](https://github.com/chipsalliance/Cores-SweRV)
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* RV32IMC
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* RV32IMC
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* Dual issue in-order 9 stage pipeline
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* Dual issue in-order 9 stage pipeline
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* 4 ALU units (2 early, 2 late)
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* 4 ALU units (2 early, 2 late)
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* :heavy_multiplication_x: *System Verilog + auto signal hookup*
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* :heavy_multiplication_x: *System Verilog + auto signal hookup*
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* :heavy_multiplication_x: *No data cache option*
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* :heavy_multiplication_x: *No data cache option*
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* :heavy_multiplication_x: *Not able to boot Linux*
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* :heavy_multiplication_x: *Not able to boot Linux*
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## Project Aims
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## Project Aims
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* Boot Linux all the way to a functional userspace environment. :heavy_check_mark:
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* Boot Linux all the way to a functional userspace environment. :heavy_check_mark:
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* Achieve competitive performance for this class of in-order machine (i.e. aim for 80% of WD SweRV CoreMark score). :heavy_check_mark:
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* Achieve competitive performance for this class of in-order machine (i.e. aim for 80% of WD SweRV CoreMark score). :heavy_check_mark:
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* Reasonable PPA / FPGA resource friendly. :heavy_check_mark:
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* Reasonable PPA / FPGA resource friendly. :heavy_check_mark:
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* Fit easily onto cheap hobbyist FPGAs (e.g. Xilinx Artix 7) without using all LUT resources and synthesize > 50MHz. :heavy_check_mark:
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* Fit easily onto cheap hobbyist FPGAs (e.g. Xilinx Artix 7) without using all LUT resources and synthesize > 50MHz. :heavy_check_mark:
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* Support various cache and TCM options. :heavy_check_mark:
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* Support various cache and TCM options. :heavy_check_mark:
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* Be constructed using readable, maintainable and documented IEEE 1364-2001 Verilog. :heavy_check_mark:
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* Be constructed using readable, maintainable and documented IEEE 1364-2001 Verilog. :heavy_check_mark:
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* Simulate in open-source tools such as Verilator and Icarus Verilog. :heavy_check_mark:
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* Simulate in open-source tools such as Verilator and Icarus Verilog. :heavy_check_mark:
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* *In later releases, add support for atomic extensions.*
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* *In later releases, add support for atomic extensions.*
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*Booting the stock Linux 5.0.0-rc8 kernel built for RV32IMA to userspace on a Digilent Arty Artix 7 with biRISC-V (with atomic instructions emulated in the bootloader);*
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*Booting the stock Linux 5.0.0-rc8 kernel built for RV32IMA to userspace on a Digilent Arty Artix 7 with biRISC-V (with atomic instructions emulated in the bootloader);*
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## Prior Work
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## Prior Work
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Based on my previous work;
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Based on my previous work;
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* Github: [http://github.com/ultraembedded/riscv](http://github.com/ultraembedded/riscv)
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* Github: [http://github.com/ultraembedded/riscv](http://github.com/ultraembedded/riscv)
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## Getting Started
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## Getting Started
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#### Cloning
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#### Cloning
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To clone this project and its dependencies;
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To clone this project and its dependencies;
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```
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```
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git clone --recursive https://github.com/ultraembedded/biriscv.git
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git clone --recursive https://github.com/ultraembedded/biriscv.git
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```
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```
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#### Running Helloworld
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#### Running Helloworld
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To run a simple test image on the core RTL using Icarus Verilog;
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To run a simple test image on the core RTL using Icarus Verilog;
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```
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```
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# Install Icarus Verilog (Debian / Ubuntu / Linux Mint)
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# Install Icarus Verilog (Debian / Ubuntu / Linux Mint)
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sudo apt-get install iverilog
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sudo apt-get install iverilog
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# [or] Install Icarus Verilog (Redhat / Centos)
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# [or] Install Icarus Verilog (Redhat / Centos)
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#sudo yum install iverilog
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#sudo yum install iverilog
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# Run a simple test image (test.elf)
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# Run a simple test image (test.elf)
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cd tb/tb_core_icarus
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cd tb/tb_core_icarus
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make
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make
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```
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```
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The expected output is;
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The expected output is;
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```
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```
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Starting bench
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Starting bench
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VCD info: dumpfile waveform.vcd opened for output.
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VCD info: dumpfile waveform.vcd opened for output.
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Test:
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Test:
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1. Initialised data
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1. Initialised data
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2. Multiply
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2. Multiply
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3. Divide
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3. Divide
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4. Shift left
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4. Shift left
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5. Shift right
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5. Shift right
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6. Shift right arithmetic
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6. Shift right arithmetic
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7. Signed comparision
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7. Signed comparision
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8. Word access
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8. Word access
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9. Byte access
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9. Byte access
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10. Comparision
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10. Comparision
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```
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```
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#### Configuration
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#### Configuration
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| Param Name | Valid Range | Description |
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| Param Name | Valid Range | Description |
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| ------------------------- |:--------------------:| ----------------------------------------------|
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| ------------------------- |:--------------------:| ----------------------------------------------|
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| SUPPORT_SUPER | 1/0 | Enable supervisor / user privilege levels. |
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| SUPPORT_SUPER | 1/0 | Enable supervisor / user privilege levels. |
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| SUPPORT_MMU | 1/0 | Enable basic memory management unit. |
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| SUPPORT_MMU | 1/0 | Enable basic memory management unit. |
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| SUPPORT_MULDIV | 1/0 | Enable HW multiply / divide (RV-M). |
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| SUPPORT_MULDIV | 1/0 | Enable HW multiply / divide (RV-M). |
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| SUPPORT_DUAL_ISSUE | 1/0 | Support superscalar operation. |
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| SUPPORT_DUAL_ISSUE | 1/0 | Support superscalar operation. |
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| SUPPORT_LOAD_BYPASS | 1/0 | Support load result bypass paths. |
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| SUPPORT_LOAD_BYPASS | 1/0 | Support load result bypass paths. |
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| SUPPORT_MUL_BYPASS | 1/0 | Support multiply result bypass paths. |
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| SUPPORT_MUL_BYPASS | 1/0 | Support multiply result bypass paths. |
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| SUPPORT_REGFILE_XILINX | 1/0 | Support Xilinx optimised register file. |
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| SUPPORT_REGFILE_XILINX | 1/0 | Support Xilinx optimised register file. |
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| SUPPORT_BRANCH_PREDICTION | 1/0 | Enable branch prediction structures. |
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| SUPPORT_BRANCH_PREDICTION | 1/0 | Enable branch prediction structures. |
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| NUM_BTB_ENTRIES | 2 - | Number of branch target buffer entries. |
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| NUM_BTB_ENTRIES | 2 - | Number of branch target buffer entries. |
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| NUM_BTB_ENTRIES_W | 1 - | Set to log2(NUM_BTB_ENTRIES). |
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| NUM_BTB_ENTRIES_W | 1 - | Set to log2(NUM_BTB_ENTRIES). |
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| NUM_BHT_ENTRIES | 2 - | Number of branch history table entries. |
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| NUM_BHT_ENTRIES | 2 - | Number of branch history table entries. |
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| NUM_BHT_ENTRIES_W | 1 - | Set to log2(NUM_BHT_ENTRIES_W). |
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| NUM_BHT_ENTRIES_W | 1 - | Set to log2(NUM_BHT_ENTRIES_W). |
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| BHT_ENABLE | 1/0 | Enable branch history table based prediction. |
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| BHT_ENABLE | 1/0 | Enable branch history table based prediction. |
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| GSHARE_ENABLE | 1/0 | Enable GSHARE branch prediction algorithm. |
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| GSHARE_ENABLE | 1/0 | Enable GSHARE branch prediction algorithm. |
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| RAS_ENABLE | 1/0 | Enable return address stack prediction. |
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| RAS_ENABLE | 1/0 | Enable return address stack prediction. |
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| NUM_RAS_ENTRIES | 2 - | Number of return stack addresses supported. |
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| NUM_RAS_ENTRIES | 2 - | Number of return stack addresses supported. |
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| NUM_RAS_ENTRIES_W | 1 - | Set to log2(NUM_RAS_ENTRIES_W). |
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| NUM_RAS_ENTRIES_W | 1 - | Set to log2(NUM_RAS_ENTRIES_W). |
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| EXTRA_DECODE_STAGE | 1/0 | Extra decode pipe stage for improved timing. |
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| EXTRA_DECODE_STAGE | 1/0 | Extra decode pipe stage for improved timing. |
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| MEM_CACHE_ADDR_MIN | 32'h0 - 32'hffffffff | Lowest cacheable memory address. |
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| MEM_CACHE_ADDR_MIN | 32'h0 - 32'hffffffff | Lowest cacheable memory address. |
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| MEM_CACHE_ADDR_MAX | 32'h0 - 32'hffffffff | Highest cacheable memory address. |
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| MEM_CACHE_ADDR_MAX | 32'h0 - 32'hffffffff | Highest cacheable memory address. |
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