#=======================================================================
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#=======================================================================
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# 6.375 Makefile for dc-synth
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# 6.375 Makefile for dc-synth
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#-----------------------------------------------------------------------
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#-----------------------------------------------------------------------
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# $Id: Makefile,v 1.2 2008-06-26 17:58:29 jamey.hicks Exp $
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# $Id: Makefile,v 1.2 2008-06-26 17:58:29 jamey.hicks Exp $
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#
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#
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# This makefile will use Synopsys Design Compiler to synthesize
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# This makefile will use Synopsys Design Compiler to synthesize
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# your RTL into a gate-level verilog netlist.
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# your RTL into a gate-level verilog netlist.
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#
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#
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default : all
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default : all
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basedir = ../..
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basedir = ../..
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#--------------------------------------------------------------------
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#--------------------------------------------------------------------
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# Sources
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# Sources
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#--------------------------------------------------------------------
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#--------------------------------------------------------------------
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# bsvclib Verilog
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# bsvclib Verilog
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bsvclibdir = $(MIT6375_HOME)/install/bsvclib
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bsvclibdir = $(MIT6375_HOME)/install/bsvclib
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bsvclibsrcs = \
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bsvclibsrcs = \
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# Verilog from prelude
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# Verilog from prelude
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preludedir = $(BLUESPECDIR)/Verilog
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preludedir = $(BLUESPECDIR)/Verilog
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preludesrcs = \
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preludesrcs = \
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$(preludedir)/FIFO2.v \
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$(preludedir)/FIFO2.v \
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$(preludedir)/RegFile.v \
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$(preludedir)/RegFile.v \
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$(preludedir)/SizedFIFO.v \
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$(preludedir)/SizedFIFO.v \
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# Verilog in source directory
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# Verilog in source directory
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vsrcdir = $(basedir)/src
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vsrcdir = $(basedir)/src
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vsrcs = \
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vsrcs = \
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# BSC generated verilog
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# BSC generated verilog
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bscdir = ../build
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bscdir = ../build
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bscsrcs = \
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bscsrcs = \
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$(bsrcdir)/mkH264.v \
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$(bsrcdir)/mkH264.v \
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$(bsrcdir)/mkEntropyDec.v \
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$(bsrcdir)/mkEntropyDec.v \
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$(bsrcdir)/mkCalc_nC.v \
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$(bsrcdir)/mkCalc_nC.v \
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$(bsrcdir)/mkInverseTrans.v \
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$(bsrcdir)/mkInverseTrans.v \
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$(bsrcdir)/mkPrediction.v \
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$(bsrcdir)/mkPrediction.v \
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$(bsrcdir)/mkDeblockFilter.v \
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$(bsrcdir)/mkDeblockFilter.v \
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$(bsrcdir)/mkBufferControl.v \
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$(bsrcdir)/mkBufferControl.v \
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$(bsrcdir)/mkInterpolator.v \
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$(bsrcdir)/mkInterpolator.v \
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$(bsrcdir)/mkbSVector.v \
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$(bsrcdir)/mkbSVector.v \
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$(bsrcdir)/mkLeftVector.v \
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$(bsrcdir)/mkLeftVector.v \
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$(bsrcdir)/mkTopVector.v \
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$(bsrcdir)/mkTopVector.v \
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$(bsrcdir)/mkWorkVectorHor.v \
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$(bsrcdir)/mkWorkVectorHor.v \
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$(bsrcdir)/mkWorkVectorVer.v \
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$(bsrcdir)/mkWorkVectorVer.v \
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$(bsrcdir)/module_cavlc_coeff_token.v \
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$(bsrcdir)/module_cavlc_coeff_token.v \
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$(bsrcdir)/module_cavlc_level_prefix.v \
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$(bsrcdir)/module_cavlc_level_prefix.v \
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$(bsrcdir)/module_cavlc_run_before.v \
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$(bsrcdir)/module_cavlc_run_before.v \
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$(bsrcdir)/module_cavlc_total_zeros.v \
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$(bsrcdir)/module_cavlc_total_zeros.v \
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$(bsrcdir)/module_expgolomb_coded_block_pattern.v \
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$(bsrcdir)/module_expgolomb_coded_block_pattern.v \
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$(bsrcdir)/module_expgolomb_codenum.v \
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$(bsrcdir)/module_expgolomb_codenum.v \
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$(bsrcdir)/module_expgolomb_numbits.v \
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$(bsrcdir)/module_expgolomb_numbits.v \
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$(bsrcdir)/module_expgolomb_signed.v \
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$(bsrcdir)/module_expgolomb_signed.v \
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$(bsrcdir)/module_expgolomb_unsigned.v \
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$(bsrcdir)/module_expgolomb_unsigned.v \
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$(bsrcdir)/module_expgolomb_codenum32.v \
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$(bsrcdir)/module_expgolomb_codenum32.v \
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$(bsrcdir)/module_expgolomb_numbits32.v \
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$(bsrcdir)/module_expgolomb_numbits32.v \
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$(bsrcdir)/module_expgolomb_signed32.v \
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$(bsrcdir)/module_expgolomb_signed32.v \
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$(bsrcdir)/module_expgolomb_unsigned32.v \
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$(bsrcdir)/module_expgolomb_unsigned32.v \
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# Specify what the toplevel verilog module is
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# Specify what the toplevel verilog module is
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toplevel = mkH264
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toplevel = mkH264
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# Specify any instantiations which should be marked don't touch
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# Specify any instantiations which should be marked don't touch
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dont_touch = \
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dont_touch = \
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#--------------------------------------------------------------------
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#--------------------------------------------------------------------
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# Build rules
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# Build rules
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#--------------------------------------------------------------------
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#--------------------------------------------------------------------
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build_suffix := $(shell date +%Y-%m-%d_%H-%M)
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build_suffix := $(shell date +%Y-%m-%d_%H-%M)
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build_dir := build-$(build_suffix)
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build_dir := build-$(build_suffix)
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curr_build_dir := current
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curr_build_dir := current
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curr_build_dir_tstamp := current/timestamp.txt
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curr_build_dir_tstamp := current/timestamp.txt
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synth_verilog := $(curr_build_dir)/synthesized.v
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synth_verilog := $(curr_build_dir)/synthesized.v
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synth_tcl := synth.tcl
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synth_tcl := synth.tcl
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libs_tcl := libs.tcl
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libs_tcl := libs.tcl
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synth_sdc := synth.sdc
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synth_sdc := synth.sdc
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scripts := $(synth_tcl) $(libs_tcl) $(synth_sdc)
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scripts := $(synth_tcl) $(libs_tcl) $(synth_sdc)
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makegen_tcl := make_generated_vars.tcl
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makegen_tcl := make_generated_vars.tcl
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libdir = $(MIT6375_HOME)/libs/tsl180/tsl18fs120
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libdir = $(MIT6375_HOME)/libs/tsl180/tsl18fs120
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synth_vars = \
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synth_vars = \
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set SEARCH_PATH { $(bvclibdir) $(preludedir) ../$(vsrcdir) ../${bscdir} }; \
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set SEARCH_PATH { $(bvclibdir) $(preludedir) ../$(vsrcdir) ../${bscdir} }; \
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set DONT_TOUCH { $(dont_touch) }; \
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set DONT_TOUCH { $(dont_touch) }; \
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set LINK_DBS $(libdir)/db/tsl18fs120_typ.db; \
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set LINK_DBS $(libdir)/db/tsl18fs120_typ.db; \
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set TARGET_DBS $(libdir)/db/tsl18fs120_typ.db; \
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set TARGET_DBS $(libdir)/db/tsl18fs120_typ.db; \
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set SYMBOL_SDBS $(libdir)/sdb/tsl18fs120_icon.sdb; \
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set SYMBOL_SDBS $(libdir)/sdb/tsl18fs120_icon.sdb; \
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set VERILOG_SRCS { $(notdir $(bsvclibsrcs) $(preludesrcs) $(vsrcs) $(bscsrcs)) }; \
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set VERILOG_SRCS { $(notdir $(bsvclibsrcs) $(preludesrcs) $(vsrcs) $(bscsrcs)) }; \
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set VERILOG_TOPLEVEL $(toplevel); \
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set VERILOG_TOPLEVEL $(toplevel); \
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define new-build-dir-cmds
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define new-build-dir-cmds
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mkdir $(build_dir)
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mkdir $(build_dir)
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rm -f $(curr_build_dir)
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rm -f $(curr_build_dir)
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ln -s $(build_dir) $(curr_build_dir)
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ln -s $(build_dir) $(curr_build_dir)
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cp $(scripts) $(curr_build_dir)
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cp $(scripts) $(curr_build_dir)
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echo '$(synth_vars)' > $(curr_build_dir)/$(makegen_tcl)
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echo '$(synth_vars)' > $(curr_build_dir)/$(makegen_tcl)
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endef
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endef
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new-build-dir :
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new-build-dir :
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$(new-build-dir-cmds)
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$(new-build-dir-cmds)
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$(synth_verilog) : $(vsrcs) $(vclibsrcs) $(scripts)
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$(synth_verilog) : $(vsrcs) $(vclibsrcs) $(scripts)
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$(new-build-dir-cmds)
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$(new-build-dir-cmds)
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cd $(curr_build_dir); \
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cd $(curr_build_dir); \
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dc_shell-xg-t -f $(synth_tcl) | tee dc.log; \
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dc_shell-xg-t -f $(synth_tcl) | tee dc.log; \
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cd ..
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cd ..
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synth : $(synth_verilog)
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synth : $(synth_verilog)
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junk +=
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junk +=
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.PHONY : synth new-build-dir
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.PHONY : synth new-build-dir
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#--------------------------------------------------------------------
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#--------------------------------------------------------------------
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# Default make target
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# Default make target
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#--------------------------------------------------------------------
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#--------------------------------------------------------------------
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all : synth
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all : synth
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#--------------------------------------------------------------------
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#--------------------------------------------------------------------
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# Clean up
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# Clean up
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#--------------------------------------------------------------------
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#--------------------------------------------------------------------
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clean :
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clean :
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rm -rf build-[0-9][0-9][0-9][0-9]-[0-9][0-9]-[0-9][0-9]_[0-9][0-9]-[0-9][0-9] \
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rm -rf build-[0-9][0-9][0-9][0-9]-[0-9][0-9]-[0-9][0-9]_[0-9][0-9]-[0-9][0-9] \
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current $(junk) *~ \#*
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current $(junk) *~ \#*
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