//----------------------------------------------------------------------//
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//----------------------------------------------------------------------//
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// The MIT License
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// The MIT License
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//
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//
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// Copyright (c) 2008 Kermin Fleming, kfleming@mit.edu
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// Copyright (c) 2008 Kermin Fleming, kfleming@mit.edu
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//
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//
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// Permission is hereby granted, free of charge, to any person
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// Permission is hereby granted, free of charge, to any person
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// obtaining a copy of this software and associated documentation
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// obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without
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// files (the "Software"), to deal in the Software without
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// restriction, including without limitation the rights to use,
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// restriction, including without limitation the rights to use,
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// copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the
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// copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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// Software is furnished to do so, subject to the following conditions:
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//
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//
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// The above copyright notice and this permission notice shall be
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// The above copyright notice and this permission notice shall be
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// included in all copies or substantial portions of the Software.
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// included in all copies or substantial portions of the Software.
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//
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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// OTHER DEALINGS IN THE SOFTWARE.
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// OTHER DEALINGS IN THE SOFTWARE.
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//----------------------------------------------------------------------//
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//----------------------------------------------------------------------//
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/*
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/*
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Copyright (c) 2008 MIT
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Copyright (c) 2008 MIT
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|
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Permission is hereby granted, free of charge, to any person
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Permission is hereby granted, free of charge, to any person
|
obtaining a copy of this software and associated documentation
|
obtaining a copy of this software and associated documentation
|
files (the "Software"), to deal in the Software without
|
files (the "Software"), to deal in the Software without
|
restriction, including without limitation the rights to use,
|
restriction, including without limitation the rights to use,
|
copy, modify, merge, publish, distribute, sublicense, and/or sell
|
copy, modify, merge, publish, distribute, sublicense, and/or sell
|
copies of the Software, and to permit persons to whom the
|
copies of the Software, and to permit persons to whom the
|
Software is furnished to do so, subject to the following
|
Software is furnished to do so, subject to the following
|
conditions:
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conditions:
|
|
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The above copyright notice and this permission notice shall be
|
The above copyright notice and this permission notice shall be
|
included in all copies or substantial portions of the Software.
|
included in all copies or substantial portions of the Software.
|
|
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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OTHER DEALINGS IN THE SOFTWARE.
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OTHER DEALINGS IN THE SOFTWARE.
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Author: Kermin Fleming
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Author: Kermin Fleming
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*/
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*/
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/* This is the top-level sorter module. It interfaces to the PLB bus, the
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/* This is the top-level sorter module. It interfaces to the PLB bus, the
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DSOCM, and the sorter core. Not much functionality, but it does have
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DSOCM, and the sorter core. Not much functionality, but it does have
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a cycle timer, and sends periodic messages back to the PPC over the
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a cycle timer, and sends periodic messages back to the PPC over the
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DSOCM
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DSOCM
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*/
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*/
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// Bluespec Lib
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// Bluespec Lib
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import FIFO::*;
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import FIFO::*;
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import GetPut::*;
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import GetPut::*;
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import Vector::*;
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import Vector::*;
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import Connectable::*;
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import Connectable::*;
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// CSG Lib
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// CSG Lib
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import PLBMasterWires::*;
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import PLBMasterWires::*;
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import BRAMInitiatorWires::*;
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import BRAMInitiatorWires::*;
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import PLBMaster::*;
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import PLBMaster::*;
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import BRAMFeeder::*;
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import BRAMFeeder::*;
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import PLBMaster::*;
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import PLBMaster::*;
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import PLBMasterDefaultParameters::*;
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import PLBMasterDefaultParameters::*;
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// Local includes
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// Local includes
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import CompressionFunction::*;
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import CompressionFunction::*;
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import CompressionFunctionLibrary::*;
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import CompressionFunctionLibrary::*;
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import MD6Parameters::*;
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import MD6Parameters::*;
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import MD6Types::*;
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import MD6Types::*;
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interface MD6Engine;
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interface MD6Engine;
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interface PLBMasterWires plbMasterWires;
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interface PLBMasterWires plbMasterWires;
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interface BRAMInitiatorWires#(Bit#(14)) bramInitiatorWires;
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interface BRAMInitiatorWires#(Bit#(14)) bramInitiatorWires;
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endinterface
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endinterface
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// Might consider making this size 8 at some point so that it jives with
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// Might consider making this size 8 at some point so that it jives with
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// other parameterizations
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// other parameterizations
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typedef 16 InterfaceRegister;
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typedef 16 InterfaceRegister;
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typedef Bit#(15) RegisterTag;
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typedef Bit#(15) RegisterTag;
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typedef enum {
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typedef enum {
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Read = 0,
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Read = 0,
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Write = 1
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Write = 1
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} Command deriving (Bits,Eq);
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} Command deriving (Bits,Eq);
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typedef 7 ControlRegisters;
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typedef 7 ControlRegisters;
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typedef TMul#(MD6_u,TDiv#(MD6_WordWidth,InterfaceRegister)) IdentifierRegisters;
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typedef TMul#(MD6_u,TDiv#(MD6_WordWidth,InterfaceRegister)) IdentifierRegisters;
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typedef TMul#(MD6_k,TDiv#(MD6_WordWidth,InterfaceRegister)) KeyRegisters;
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typedef TMul#(MD6_k,TDiv#(MD6_WordWidth,InterfaceRegister)) KeyRegisters;
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typedef 2 SourceRegisters;
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typedef 2 SourceRegisters;
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typedef 2 DestinationRegisters;
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typedef 2 DestinationRegisters;
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typedef 0 RoundRegister;
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typedef 0 RoundRegister;
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typedef 1 TreeHeightRegister;
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typedef 1 TreeHeightRegister;
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typedef 2 LastCompressionRegister;
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typedef 2 LastCompressionRegister;
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typedef 3 PaddingBitsRegister;
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typedef 3 PaddingBitsRegister;
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typedef 4 KeyLengthRegister;
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typedef 4 KeyLengthRegister;
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typedef 5 DigestLengthRegister;
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typedef 5 DigestLengthRegister;
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typedef 6 CompressionFunctionStatus;
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typedef 6 CompressionFunctionStatus;
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typedef 7 KeyRegisterBase;
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typedef 7 KeyRegisterBase;
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typedef TAdd#(ControlRegisters,KeyRegisters) IdentifierRegisterBase;
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typedef TAdd#(ControlRegisters,KeyRegisters) IdentifierRegisterBase;
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typedef TAdd#(ControlRegisters, TAdd#(KeyRegisters,IdentifierRegisters)) SourceRegisterBase;
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typedef TAdd#(ControlRegisters, TAdd#(KeyRegisters,IdentifierRegisters)) SourceRegisterBase;
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typedef TAdd#(TAdd#(ControlRegisters,IdentifierRegisters), TAdd#(KeyRegisters,SourceRegisters)) DestinationRegisterBase;
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typedef TAdd#(TAdd#(ControlRegisters,IdentifierRegisters), TAdd#(KeyRegisters,SourceRegisters)) DestinationRegisterBase;
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typedef TAdd#(IdentifierRegisters,TAdd#(TAdd#(ControlRegisters,DestinationRegisters), TAdd#(KeyRegisters,SourceRegisters))) TotalRegisters;
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typedef TAdd#(IdentifierRegisters,TAdd#(TAdd#(ControlRegisters,DestinationRegisters), TAdd#(KeyRegisters,SourceRegisters))) TotalRegisters;
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typedef TDiv#(TMul#(SizeOf#(BusWord),BeatsPerBurst), SizeOf#(MD6Word)) MD6WordsPerBurst;
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typedef TDiv#(TMul#(SizeOf#(BusWord),BeatsPerBurst), SizeOf#(MD6Word)) MD6WordsPerBurst;
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typedef 32'hC0000 MD6CommunicationConstant;
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typedef 32'hC0000 MD6CommunicationConstant;
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typedef struct {
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typedef struct {
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Command command;
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Command command;
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RegisterTag regTag;
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RegisterTag regTag;
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Bit#(InterfaceRegister) payload;
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Bit#(InterfaceRegister) payload;
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} IOCommand deriving (Bits,Eq);
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} IOCommand deriving (Bits,Eq);
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typedef enum {
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typedef enum {
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Idle,
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Idle,
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Load
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Load
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} LoadState deriving (Bits,Eq);
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} LoadState deriving (Bits,Eq);
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typedef enum {
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typedef enum {
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Idle,
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Idle,
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Store
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Store
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} StoreState deriving (Bits,Eq);
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} StoreState deriving (Bits,Eq);
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(*synthesize*)
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(*synthesize*)
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module mkCompressionFunction64 (CompressionFunction#(64));
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module mkCompressionFunction64 (CompressionFunction#(64));
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let m <- mkMult16CompressionFunction;
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let m <- mkMult16CompressionFunction;
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return m;
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return m;
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endmodule
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endmodule
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(*synthesize*)
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(*synthesize*)
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module mkCompressionFunction48 (CompressionFunction#(48));
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module mkCompressionFunction48 (CompressionFunction#(48));
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let m <- mkMult16CompressionFunction;
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let m <- mkMult16CompressionFunction;
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return m;
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return m;
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endmodule
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endmodule
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(*synthesize*)
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(*synthesize*)
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module mkCompressionFunction32 (CompressionFunction#(32));
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module mkCompressionFunction32 (CompressionFunction#(32));
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let m <- mkMult16CompressionFunction;
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let m <- mkMult16CompressionFunction;
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return m;
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return m;
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endmodule
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endmodule
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(*synthesize*)
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(*synthesize*)
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module mkCompressionFunction16 (CompressionFunction#(16));
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module mkCompressionFunction16 (CompressionFunction#(16));
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let m <- mkSimpleCompressionFunction;
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let m <- mkSimpleCompressionFunction;
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return m;
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return m;
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endmodule
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endmodule
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(*synthesize*)
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(*synthesize*)
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module mkCompressionFunction8 (CompressionFunction#(8));
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module mkCompressionFunction8 (CompressionFunction#(8));
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let m <- mkSimpleCompressionFunction;
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let m <- mkSimpleCompressionFunction;
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return m;
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return m;
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endmodule
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endmodule
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(*synthesize*)
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(*synthesize*)
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module mkCompressionFunction4 (CompressionFunction#(4));
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module mkCompressionFunction4 (CompressionFunction#(4));
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let m <- mkSimpleCompressionFunction;
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let m <- mkSimpleCompressionFunction;
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return m;
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return m;
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endmodule
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endmodule
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(*synthesize*)
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(*synthesize*)
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module mkCompressionFunction2 (CompressionFunction#(2));
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module mkCompressionFunction2 (CompressionFunction#(2));
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let m <- mkSimpleCompressionFunction;
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let m <- mkSimpleCompressionFunction;
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return m;
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return m;
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endmodule
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endmodule
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(*synthesize*)
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(*synthesize*)
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module mkCompressionFunction1 (CompressionFunction#(1));
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module mkCompressionFunction1 (CompressionFunction#(1));
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let m <- mkSimpleCompressionFunction;
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let m <- mkSimpleCompressionFunction;
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return m;
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return m;
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endmodule
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endmodule
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module mkMD6Engine (MD6Engine);
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module mkMD6Engine (MD6Engine);
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Feeder feeder <- mkBRAMFeeder();
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Feeder feeder <- mkBRAMFeeder();
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PLBMaster plbMaster <- mkPLBMaster;
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PLBMaster plbMaster <- mkPLBMaster;
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CompressionFunction#(4) compressionFunction <- mkSimpleCompressionFunction;
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CompressionFunction#(4) compressionFunction <- mkSimpleCompressionFunction;
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FIFO#(PPCMessage) outputFIFO <- mkFIFO;
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FIFO#(PPCMessage) outputFIFO <- mkFIFO;
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Vector#(TotalRegisters, Reg#(Bit#(InterfaceRegister))) interfaceRegisters <-
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Vector#(TotalRegisters, Reg#(Bit#(InterfaceRegister))) interfaceRegisters <-
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replicateM(mkReg(0));
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replicateM(mkReg(0));
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// Hook Control, PLBMaster and MD6 engine components together.
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// Hook Control, PLBMaster and MD6 engine components together.
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// This solution WILL NOT WORK for multiple Compression functions
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// This solution WILL NOT WORK for multiple Compression functions
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mkConnection(plbMaster.wordInput.put, compressionFunction.outputWord);
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mkConnection(plbMaster.wordInput.put, compressionFunction.outputWord);
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mkConnection(compressionFunction.inputWord,plbMaster.wordOutput.get);
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mkConnection(compressionFunction.inputWord,plbMaster.wordOutput.get);
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mkConnection(feeder.ppcMessageInput.put,(fifoToGet(outputFIFO)).get);
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mkConnection(feeder.ppcMessageInput.put,(fifoToGet(outputFIFO)).get);
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Reg#(Bit#(TAdd#(1,TDiv#(MD6_b,MD6WordsPerBurst)))) loadCount <- mkReg(0);
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Reg#(Bit#(TAdd#(1,TDiv#(MD6_b,MD6WordsPerBurst)))) loadCount <- mkReg(0);
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Reg#(Bit#(TAdd#(1,TDiv#(MD6_c,MD6WordsPerBurst)))) storeCount <- mkReg(0);
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Reg#(Bit#(TAdd#(1,TDiv#(MD6_c,MD6WordsPerBurst)))) storeCount <- mkReg(0);
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Reg#(LoadState) loadState <- mkReg(Idle);
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Reg#(LoadState) loadState <- mkReg(Idle);
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Reg#(StoreState) storeState <- mkReg(Idle);
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Reg#(StoreState) storeState <- mkReg(Idle);
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FIFO#(IOCommand) incomingCommands <- mkFIFO;
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FIFO#(IOCommand) incomingCommands <- mkFIFO;
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function IOCommand extractIOCommand(PPCMessage ppcMessage);
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function IOCommand extractIOCommand(PPCMessage ppcMessage);
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IOCommand command = IOCommand {command: unpack(ppcMessage[31]),
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IOCommand command = IOCommand {command: unpack(ppcMessage[31]),
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regTag: ppcMessage[30:16],
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regTag: ppcMessage[30:16],
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payload: ppcMessage[15:0]};
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payload: ppcMessage[15:0]};
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return command;
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return command;
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endfunction
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endfunction
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// This function may require its own unit test
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// This function may require its own unit test
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// It should convert interface words to MD6 Words
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// It should convert interface words to MD6 Words
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function Vector#(length,MD6Word) convertWords(
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function Vector#(length,MD6Word) convertWords(
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Vector#(TMul#(length,TDiv#(MD6_WordWidth,InterfaceRegister)),Bit#(InterfaceRegister)) inVector);
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Vector#(TMul#(length,TDiv#(MD6_WordWidth,InterfaceRegister)),Bit#(InterfaceRegister)) inVector);
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Vector#(length,MD6Word) outVector = newVector;
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Vector#(length,MD6Word) outVector = newVector;
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for(Integer totalNumber = 0;
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for(Integer totalNumber = 0;
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totalNumber < valueof(length);
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totalNumber < valueof(length);
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totalNumber = totalNumber + 1)
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totalNumber = totalNumber + 1)
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begin
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begin
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Vector#(TDiv#(MD6_WordWidth,InterfaceRegister),Bit#(InterfaceRegister)) wordVector = newVector;
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Vector#(TDiv#(MD6_WordWidth,InterfaceRegister),Bit#(InterfaceRegister)) wordVector = newVector;
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for(Integer wordsInMD6Word = 0;
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for(Integer wordsInMD6Word = 0;
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wordsInMD6Word < valueof(TDiv#(MD6_WordWidth,InterfaceRegister));
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wordsInMD6Word < valueof(TDiv#(MD6_WordWidth,InterfaceRegister));
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wordsInMD6Word = wordsInMD6Word + 1)
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wordsInMD6Word = wordsInMD6Word + 1)
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begin
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begin
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wordVector[wordsInMD6Word] = inVector[totalNumber*valueof(TDiv#(MD6_WordWidth,InterfaceRegister))
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wordVector[wordsInMD6Word] = inVector[totalNumber*valueof(TDiv#(MD6_WordWidth,InterfaceRegister))
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+wordsInMD6Word];
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+wordsInMD6Word];
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end
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end
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outVector[totalNumber] = unpack(pack(wordVector)); // is this sane?
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outVector[totalNumber] = unpack(pack(wordVector)); // is this sane?
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end
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end
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return outVector;
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return outVector;
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endfunction
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endfunction
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rule getCommand;
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rule getCommand;
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PPCMessage msg <- feeder.ppcMessageOutput.get;
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PPCMessage msg <- feeder.ppcMessageOutput.get;
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IOCommand command = extractIOCommand(msg);
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IOCommand command = extractIOCommand(msg);
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incomingCommands.enq(command);
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incomingCommands.enq(command);
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endrule
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endrule
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// Writing to the CompressionFunctionStatus means kickoff a compression operation
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// Writing to the CompressionFunctionStatus means kickoff a compression operation
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// Reading from it will grab the current status of the Compression Engine
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// Reading from it will grab the current status of the Compression Engine
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|
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rule processWrite(incomingCommands.first.command == Write);
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rule processWrite(incomingCommands.first.command == Write);
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incomingCommands.deq;
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incomingCommands.deq;
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|
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if(fromInteger(valueof(CompressionFunctionStatus)) == incomingCommands.first.regTag)
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if(fromInteger(valueof(CompressionFunctionStatus)) == incomingCommands.first.regTag)
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begin
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begin
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// we can leave this unguarded because the properties of the compression function
|
// we can leave this unguarded because the properties of the compression function
|
// will prevent doing nasty things like confusing the order of memory accesses.
|
// will prevent doing nasty things like confusing the order of memory accesses.
|
let controlWord = makeControlWord(truncate(interfaceRegisters[valueof(RoundRegister)]),
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let controlWord = makeControlWord(truncate(interfaceRegisters[valueof(RoundRegister)]),
|
truncate(interfaceRegisters[valueof(TreeHeightRegister)]),
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truncate(interfaceRegisters[valueof(TreeHeightRegister)]),
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truncate(interfaceRegisters[valueof(LastCompressionRegister)]),
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truncate(interfaceRegisters[valueof(LastCompressionRegister)]),
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truncate(interfaceRegisters[valueof(PaddingBitsRegister)]),
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truncate(interfaceRegisters[valueof(PaddingBitsRegister)]),
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truncate(interfaceRegisters[valueof(KeyLengthRegister)]),
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truncate(interfaceRegisters[valueof(KeyLengthRegister)]),
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truncate(interfaceRegisters[valueof(DigestLengthRegister)]));
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truncate(interfaceRegisters[valueof(DigestLengthRegister)]));
|
|
|
compressionFunction.start(convertWords(takeAt(valueof(IdentifierRegisterBase),readVReg(interfaceRegisters))),
|
compressionFunction.start(convertWords(takeAt(valueof(IdentifierRegisterBase),readVReg(interfaceRegisters))),
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controlWord,
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controlWord,
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convertWords(takeAt(valueof(KeyRegisterBase),readVReg(interfaceRegisters))));
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convertWords(takeAt(valueof(KeyRegisterBase),readVReg(interfaceRegisters))));
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loadState <= Load;
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loadState <= Load;
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loadCount <= 0;
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loadCount <= 0;
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end
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end
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else
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else
|
begin
|
begin
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interfaceRegisters[incomingCommands.first.regTag] <= incomingCommands.first.payload;
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interfaceRegisters[incomingCommands.first.regTag] <= incomingCommands.first.payload;
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end
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end
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endrule
|
endrule
|
|
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rule processRead(incomingCommands.first.command == Read);
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rule processRead(incomingCommands.first.command == Read);
|
incomingCommands.deq;
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incomingCommands.deq;
|
|
|
// This is a bit ugly, and we should possibly fix it.
|
// This is a bit ugly, and we should possibly fix it.
|
if(fromInteger(valueof(CompressionFunctionStatus)) == incomingCommands.first.regTag)
|
if(fromInteger(valueof(CompressionFunctionStatus)) == incomingCommands.first.regTag)
|
begin
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begin
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outputFIFO.enq(fromInteger(valueof(MD6CommunicationConstant))|zeroExtend(compressionFunction.status));
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outputFIFO.enq(fromInteger(valueof(MD6CommunicationConstant))|zeroExtend(compressionFunction.status));
|
end
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end
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else
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else
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begin
|
begin
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outputFIFO.enq(fromInteger(valueof(MD6CommunicationConstant))|zeroExtend((interfaceRegisters[incomingCommands.first.regTag])));
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outputFIFO.enq(fromInteger(valueof(MD6CommunicationConstant))|zeroExtend((interfaceRegisters[incomingCommands.first.regTag])));
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end
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end
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|
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endrule
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endrule
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|
|
|
|
|
|
|
|
// Probably should handle non-fitting burst sizes. But, don't have to
|
// Probably should handle non-fitting burst sizes. But, don't have to
|
// for now.
|
// for now.
|
if(valueof(TotalRegisters) != 47)
|
if(valueof(TotalRegisters) != 47)
|
begin
|
begin
|
error("Total Registers: %d\n",valueof(TotalRegisters));
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error("Total Registers: %d\n",valueof(TotalRegisters));
|
end
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end
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|
|
if(valueof(MD6_b)%valueof(MD6WordsPerBurst) != 0)
|
if(valueof(MD6_b)%valueof(MD6WordsPerBurst) != 0)
|
begin
|
begin
|
error("MD6_b:%d not divisible by MD6WordsPerBurst:%d",valueof(MD6_b), valueof(MD6WordsPerBurst));
|
error("MD6_b:%d not divisible by MD6WordsPerBurst:%d",valueof(MD6_b), valueof(MD6WordsPerBurst));
|
end
|
end
|
|
|
if(valueof(MD6_c)%valueof(MD6WordsPerBurst) != 0)
|
if(valueof(MD6_c)%valueof(MD6WordsPerBurst) != 0)
|
begin
|
begin
|
error("MD6_c:%d not divisible by MD6WordsPerBurst:%d",valueof(MD6_c), valueof(MD6WordsPerBurst));
|
error("MD6_c:%d not divisible by MD6WordsPerBurst:%d",valueof(MD6_c), valueof(MD6WordsPerBurst));
|
end
|
end
|
|
|
rule issueLoads(loadState == Load);
|
rule issueLoads(loadState == Load);
|
if(loadCount + 1 == fromInteger(valueof(MD6_b)/valueof(MD6WordsPerBurst)))
|
if(loadCount + 1 == fromInteger(valueof(MD6_b)/valueof(MD6WordsPerBurst)))
|
begin
|
begin
|
loadState <= Idle;
|
loadState <= Idle;
|
storeState <= Store;
|
storeState <= Store;
|
storeCount <= 0;
|
storeCount <= 0;
|
end
|
end
|
loadCount <= loadCount + 1;
|
loadCount <= loadCount + 1;
|
BlockAddr refAddr = truncateLSB({interfaceRegisters[valueof(SourceRegisterBase)+1],
|
BlockAddr refAddr = truncateLSB({interfaceRegisters[valueof(SourceRegisterBase)+1],
|
interfaceRegisters[valueof(SourceRegisterBase)]})
|
interfaceRegisters[valueof(SourceRegisterBase)]})
|
+ (zeroExtend(loadCount) << (valueof(TLog#(WordsPerBurst))));
|
+ (zeroExtend(loadCount) << (valueof(TLog#(WordsPerBurst))));
|
|
|
plbMaster.plbMasterCommandInput.put(tagged LoadPage refAddr);
|
plbMaster.plbMasterCommandInput.put(tagged LoadPage refAddr);
|
endrule
|
endrule
|
|
|
|
|
|
|
rule issueStores(storeState == Store);
|
rule issueStores(storeState == Store);
|
if(storeCount + 1 == fromInteger(valueof(MD6_c)/valueof(MD6WordsPerBurst)))
|
if(storeCount + 1 == fromInteger(valueof(MD6_c)/valueof(MD6WordsPerBurst)))
|
begin
|
begin
|
storeState <= Idle;
|
storeState <= Idle;
|
end
|
end
|
storeCount <= storeCount + 1;
|
storeCount <= storeCount + 1;
|
|
|
BlockAddr refAddr = truncateLSB({interfaceRegisters[valueof(DestinationRegisterBase)+1],
|
BlockAddr refAddr = truncateLSB({interfaceRegisters[valueof(DestinationRegisterBase)+1],
|
interfaceRegisters[valueof(DestinationRegisterBase)]})
|
interfaceRegisters[valueof(DestinationRegisterBase)]})
|
+ (zeroExtend(storeCount) << (valueof(TLog#(WordsPerBurst))));
|
+ (zeroExtend(storeCount) << (valueof(TLog#(WordsPerBurst))));
|
|
|
plbMaster.plbMasterCommandInput.put(tagged StorePage refAddr);
|
plbMaster.plbMasterCommandInput.put(tagged StorePage refAddr);
|
endrule
|
endrule
|
|
|
interface plbMasterWires = plbMaster.plbMasterWires;
|
interface plbMasterWires = plbMaster.plbMasterWires;
|
interface bramInitiatorWires = feeder.bramInitiatorWires;
|
interface bramInitiatorWires = feeder.bramInitiatorWires;
|
|
|
|
|
