-------------------------------------------------------------------
|
-------------------------------------------------------------------
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-- --
|
-- --
|
-- Copyright (C) 2013 Author and VariStream Studio --
|
-- Copyright (C) 2013 Author and VariStream Studio --
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-- Author : Yu Peng --
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-- Author : Yu Peng --
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-- --
|
-- --
|
-- This source file may be used and distributed without --
|
-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
|
-- restriction provided that this copyright statement is not --
|
-- removed from the file and that any derivative work contains --
|
-- removed from the file and that any derivative work contains --
|
-- the original copyright notice and the associated disclaimer. --
|
-- the original copyright notice and the associated disclaimer. --
|
-- --
|
-- --
|
-- This source file is free software; you can redistribute it --
|
-- This source file is free software; you can redistribute it --
|
-- and/or modify it under the terms of the GNU Lesser General --
|
-- and/or modify it under the terms of the GNU Lesser General --
|
-- Public License as published by the Free Software Foundation; --
|
-- Public License as published by the Free Software Foundation; --
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-- either version 2.1 of the License, or (at your option) any --
|
-- either version 2.1 of the License, or (at your option) any --
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-- later version. --
|
-- later version. --
|
-- --
|
-- --
|
-- This source is distributed in the hope that it will be --
|
-- This source is distributed in the hope that it will be --
|
-- useful, but WITHOUT ANY WARRANTY; without even the implied --
|
-- useful, but WITHOUT ANY WARRANTY; without even the implied --
|
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
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-- PURPOSE. See the GNU Lesser General Public License for more --
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-- PURPOSE. See the GNU Lesser General Public License for more --
|
-- details. --
|
-- details. --
|
-- --
|
-- --
|
-- You should have received a copy of the GNU Lesser General --
|
-- You should have received a copy of the GNU Lesser General --
|
-- Public License along with this source; if not, download it --
|
-- Public License along with this source; if not, download it --
|
-- from http://www.opencores.org/lgpl.shtml --
|
-- from http://www.opencores.org/lgpl.shtml --
|
-- --
|
-- --
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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|
|
library hotan;
|
|
use hotan.sha_256_pkg.all;
|
|
library ieee;
|
library ieee;
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use ieee.NUMERIC_STD.all;
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use ieee.NUMERIC_STD.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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|
|
|
use work.sha_256_pkg.all;
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|
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-- Add your library and packages declaration here ...
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-- Add your library and packages declaration here ...
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|
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entity sha_256_chunk_tb is
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entity sha_256_chunk_tb is
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end sha_256_chunk_tb;
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end sha_256_chunk_tb;
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architecture TB_ARCHITECTURE of sha_256_chunk_tb is
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architecture TB_ARCHITECTURE of sha_256_chunk_tb is
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-- Component declaration of the tested unit
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-- Component declaration of the tested unit
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component sha_256_chunk
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component sha_256_chunk
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generic(
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generic(
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gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');
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gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');
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gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1');
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gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1');
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gBASE_DELAY : integer := 3;
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gBASE_DELAY : integer := 3;
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gOUT_VALID_GEN : boolean := false;
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gOUT_VALID_GEN : boolean := false;
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gUSE_BRAM_AS_LARGE_SHIFTREG : boolean := false
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gUSE_BRAM_AS_LARGE_SHIFTREG : boolean := false
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);
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);
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port(
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port(
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iClk : in STD_LOGIC;
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iClk : in STD_LOGIC;
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iRst_async : in STD_LOGIC;
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iRst_async : in STD_LOGIC;
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iValid : in STD_LOGIC;
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iValid : in STD_LOGIC;
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ivMsgDword : in tDwordArray(0 to 15);
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ivMsgDword : in tDwordArray(0 to 15);
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ivH0 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH0 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH1 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH1 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH2 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH2 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH3 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH3 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH4 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH4 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH5 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH5 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH6 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH6 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH7 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH7 : in STD_LOGIC_VECTOR(31 downto 0);
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ovH0 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH0 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH1 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH1 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH2 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH2 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH3 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH3 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH4 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH4 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH5 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH5 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH6 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH6 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH7 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH7 : out STD_LOGIC_VECTOR(31 downto 0);
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oValid : out std_logic);
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oValid : out std_logic);
|
end component;
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end component;
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|
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-- Stimulus signals - signals mapped to the input and inout ports of tested entity
|
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
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signal iClk : STD_LOGIC := '1';
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signal iClk : STD_LOGIC := '1';
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signal iRst_async : STD_LOGIC := '1';
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signal iRst_async : STD_LOGIC := '1';
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signal iValid : STD_LOGIC := '0';
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signal iValid : STD_LOGIC := '0';
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signal ivMsgDword : tDwordArray(0 to 15) := (others=>(others=>'0'));
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signal ivMsgDword : tDwordArray(0 to 15) := (others=>(others=>'0'));
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signal ivH0 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH0 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH1 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH1 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH2 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH2 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH3 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH3 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH4 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH4 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH5 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH5 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH6 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH6 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH7 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ivH7 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal oValid : std_logic;
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signal oValid : std_logic;
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|
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-- Observed signals - signals mapped to the output ports of tested entity
|
-- Observed signals - signals mapped to the output ports of tested entity
|
|
|
-- Add your code here ...
|
-- Add your code here ...
|
|
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constant cTEST_NUM : integer := 3;
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constant cTEST_NUM : integer := 3;
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type tTEST_MSG is array(0 to cTEST_NUM - 1) of tDwordArray(0 to 15);
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type tTEST_MSG is array(0 to cTEST_NUM - 1) of tDwordArray(0 to 15);
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type tTEST_RESULT is array(0 to cTEST_NUM - 1) of tDwordArray(0 to 7);
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type tTEST_RESULT is array(0 to cTEST_NUM - 1) of tDwordArray(0 to 7);
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-- The test string length must <= 63
|
-- The test string length must <= 63
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constant cTEST_STR_00 : string := "";
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constant cTEST_STR_00 : string := "";
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constant cTEST_STR_01 : string := "The quick brown fox jumps over the lazy dog";
|
constant cTEST_STR_01 : string := "The quick brown fox jumps over the lazy dog";
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constant cTEST_STR_02 : string := "The quick brown fox jumps over the lazy dog.";
|
constant cTEST_STR_02 : string := "The quick brown fox jumps over the lazy dog.";
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|
|
constant cTEST_MSG : tTEST_MSG := (
|
constant cTEST_MSG : tTEST_MSG := (
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conv_str_to_msg(cTEST_STR_00),
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conv_str_to_msg(cTEST_STR_00),
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conv_str_to_msg(cTEST_STR_01),
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conv_str_to_msg(cTEST_STR_01),
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conv_str_to_msg(cTEST_STR_02)
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conv_str_to_msg(cTEST_STR_02)
|
);
|
);
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|
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constant cTEST_RESULT : tTEST_RESULT := (
|
constant cTEST_RESULT : tTEST_RESULT := (
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(X"e3b0c442", X"98fc1c14", X"9afbf4c8", X"996fb924", X"27ae41e4", X"649b934c", X"a495991b", X"7852b855"),
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(X"e3b0c442", X"98fc1c14", X"9afbf4c8", X"996fb924", X"27ae41e4", X"649b934c", X"a495991b", X"7852b855"),
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(X"D7A8FBB3", X"07D78094", X"69CA9ABC", X"B0082E4F", X"8D5651E4", X"6D3CDB76", X"2D02D0BF", X"37C9E592"),
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(X"D7A8FBB3", X"07D78094", X"69CA9ABC", X"B0082E4F", X"8D5651E4", X"6D3CDB76", X"2D02D0BF", X"37C9E592"),
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(X"EF537F25", X"C895BFA7", X"82526529", X"A9B63D97", X"AA631564", X"D5D789C2", X"B765448C", X"8635FB6C")
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(X"EF537F25", X"C895BFA7", X"82526529", X"A9B63D97", X"AA631564", X"D5D789C2", X"B765448C", X"8635FB6C")
|
);
|
);
|
|
|
constant cCLK_PERIOD : time := 10 ns;
|
constant cCLK_PERIOD : time := 10 ns;
|
constant cRESET_INTERVAL : time := 71 ns;
|
constant cRESET_INTERVAL : time := 71 ns;
|
constant cSTRAT_TEST : integer := 19;
|
constant cSTRAT_TEST : integer := 19;
|
|
|
|
|
signal ovH : tDwordArray(0 to 7) := (others=>(others=>'0'));
|
signal ovH : tDwordArray(0 to 7) := (others=>(others=>'0'));
|
|
|
signal siTestInCnt : integer := 0;
|
signal siTestInCnt : integer := 0;
|
signal siTestOutCnt : integer := 0;
|
signal siTestOutCnt : integer := 0;
|
|
|
signal svResultMatch : std_logic_vector(0 to cTEST_NUM - 1) := (others=>'0');
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signal svResultMatch : std_logic_vector(0 to cTEST_NUM - 1) := (others=>'0');
|
|
|
begin
|
begin
|
|
|
-- Unit Under Test port map
|
-- Unit Under Test port map
|
UUT : sha_256_chunk
|
UUT : sha_256_chunk
|
generic map(
|
generic map(
|
gMSG_IS_CONSTANT => (others=>'0'),
|
gMSG_IS_CONSTANT => (others=>'0'),
|
gH_IS_CONST => (others=>'0'),
|
gH_IS_CONST => (others=>'0'),
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gBASE_DELAY => 1,
|
gBASE_DELAY => 1,
|
gOUT_VALID_GEN => true
|
gOUT_VALID_GEN => true
|
)
|
)
|
port map (
|
port map (
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iClk => iClk,
|
iClk => iClk,
|
iRst_async => iRst_async,
|
iRst_async => iRst_async,
|
iValid => iValid,
|
iValid => iValid,
|
ivMsgDword => ivMsgDword,
|
ivMsgDword => ivMsgDword,
|
ivH0 => ivH0,
|
ivH0 => ivH0,
|
ivH1 => ivH1,
|
ivH1 => ivH1,
|
ivH2 => ivH2,
|
ivH2 => ivH2,
|
ivH3 => ivH3,
|
ivH3 => ivH3,
|
ivH4 => ivH4,
|
ivH4 => ivH4,
|
ivH5 => ivH5,
|
ivH5 => ivH5,
|
ivH6 => ivH6,
|
ivH6 => ivH6,
|
ivH7 => ivH7,
|
ivH7 => ivH7,
|
ovH0 => ovH(0),
|
ovH0 => ovH(0),
|
ovH1 => ovH(1),
|
ovH1 => ovH(1),
|
ovH2 => ovH(2),
|
ovH2 => ovH(2),
|
ovH3 => ovH(3),
|
ovH3 => ovH(3),
|
ovH4 => ovH(4),
|
ovH4 => ovH(4),
|
ovH5 => ovH(5),
|
ovH5 => ovH(5),
|
ovH6 => ovH(6),
|
ovH6 => ovH(6),
|
ovH7 => ovH(7),
|
ovH7 => ovH(7),
|
oValid => oValid
|
oValid => oValid
|
);
|
);
|
|
|
-- Add your stimulus here ...
|
-- Add your stimulus here ...
|
iClk <= not iClk after (cCLK_PERIOD / 2);
|
iClk <= not iClk after (cCLK_PERIOD / 2);
|
iRst_async <= '0' after cRESET_INTERVAL;
|
iRst_async <= '0' after cRESET_INTERVAL;
|
|
|
iValid <= '1' after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), '0' after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
iValid <= '1' after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), '0' after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH0 <= X"6a09e667" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH0 <= X"6a09e667" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH1 <= X"bb67ae85" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH1 <= X"bb67ae85" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH2 <= X"3c6ef372" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH2 <= X"3c6ef372" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH3 <= X"a54ff53a" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH3 <= X"a54ff53a" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH4 <= X"510e527f" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH4 <= X"510e527f" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH5 <= X"9b05688c" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH5 <= X"9b05688c" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH6 <= X"1f83d9ab" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH6 <= X"1f83d9ab" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH7 <= X"5be0cd19" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
ivH7 <= X"5be0cd19" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
|
|
|
process(iClk, iRst_async)
|
process(iClk, iRst_async)
|
begin
|
begin
|
if iRst_async = '1' then
|
if iRst_async = '1' then
|
siTestInCnt <= 0;
|
siTestInCnt <= 0;
|
siTestOutCnt <= 0;
|
siTestOutCnt <= 0;
|
svResultMatch <= (others=>'0');
|
svResultMatch <= (others=>'0');
|
elsif rising_edge(iClk) then
|
elsif rising_edge(iClk) then
|
if iValid = '1' then
|
if iValid = '1' then
|
siTestInCnt <= siTestInCnt + 1 after 1 ns;
|
siTestInCnt <= siTestInCnt + 1 after 1 ns;
|
end if;
|
end if;
|
|
|
if oValid = '1' then
|
if oValid = '1' then
|
siTestOutCnt <= siTestOutCnt + 1;
|
siTestOutCnt <= siTestOutCnt + 1;
|
end if;
|
end if;
|
|
|
if oValid = '1' then
|
if oValid = '1' then
|
for i in 0 to cTEST_NUM - 1 loop
|
for i in 0 to cTEST_NUM - 1 loop
|
if i = siTestOutCnt then
|
if i = siTestOutCnt then
|
if ovH = cTEST_RESULT(i) then
|
if ovH = cTEST_RESULT(i) then
|
svResultMatch(i) <= '1';
|
svResultMatch(i) <= '1';
|
else
|
else
|
svResultMatch(i) <= '0';
|
svResultMatch(i) <= '0';
|
end if;
|
end if;
|
|
|
assert ovH = cTEST_RESULT(i)
|
assert ovH = cTEST_RESULT(i)
|
report "The test " & integer'image(i) & " failed"
|
report "The test " & integer'image(i) & " failed"
|
severity ERROR;
|
severity ERROR;
|
end if;
|
end if;
|
end loop;
|
end loop;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
process(iValid, siTestInCnt)
|
process(iValid, siTestInCnt)
|
begin
|
begin
|
if iValid = '0' or siTestInCnt >= cTEST_NUM then
|
if iValid = '0' or siTestInCnt >= cTEST_NUM then
|
ivMsgDword <= (others=>(others=>'0'));
|
ivMsgDword <= (others=>(others=>'0'));
|
else
|
else
|
ivMsgDword <= cTEST_MSG(siTestInCnt);
|
ivMsgDword <= cTEST_MSG(siTestInCnt);
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end TB_ARCHITECTURE;
|
end TB_ARCHITECTURE;
|
|
|
configuration TESTBENCH_FOR_sha_256_chunk of sha_256_chunk_tb is
|
configuration TESTBENCH_FOR_sha_256_chunk of sha_256_chunk_tb is
|
for TB_ARCHITECTURE
|
for TB_ARCHITECTURE
|
for UUT : sha_256_chunk
|
for UUT : sha_256_chunk
|
use entity work.sha_256_chunk(behavioral);
|
use entity work.sha_256_chunk(behavioral);
|
end for;
|
end for;
|
end for;
|
end for;
|
end TESTBENCH_FOR_sha_256_chunk;
|
end TESTBENCH_FOR_sha_256_chunk;
|
|
|
|
|
