-- Copyright (c) 2013 VariStream
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-------------------------------------------------------------------
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-- Author : Yu Peng
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-- --
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-- Notes: Generates a "synchronous" reset from the async global reset
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-- Copyright (C) 2013 Author and VariStream Studio --
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-- Author : Yu Peng --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer. --
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-- --
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-- This source file is free software; you can redistribute it --
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-- and/or modify it under the terms of the GNU Lesser General --
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-- Public License as published by the Free Software Foundation; --
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-- either version 2.1 of the License, or (at your option) any --
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-- later version. --
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-- --
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-- This source is distributed in the hope that it will be --
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-- useful, but WITHOUT ANY WARRANTY; without even the implied --
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
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-- PURPOSE. See the GNU Lesser General Public License for more --
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-- details. --
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-- --
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-- You should have received a copy of the GNU Lesser General --
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-- Public License along with this source; if not, download it --
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-- from http://www.opencores.org/lgpl.shtml --
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-- --
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-------------------------------------------------------------------
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-- Notes:
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-- Generates a "synchronous" reset from the async global
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-- reset.
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-------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_unsigned.all;
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entity SyncReset is
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entity SyncReset is
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port(
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port(
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iClk : in std_logic; -- Clock domain that the reset should be resynchronyze to
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iClk : in std_logic; -- Clock domain that the reset should be resynchronyze to
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iAsyncReset : in std_logic; -- Asynchronous reset that should be resynchronyse
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iAsyncReset : in std_logic; -- Asynchronous reset that should be resynchronyse
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oSyncReset : out std_logic -- Synchronous reset output
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oSyncReset : out std_logic -- Synchronous reset output
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);
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);
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end SyncReset;
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end SyncReset;
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architecture SyncReset of SyncReset is
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architecture SyncReset of SyncReset is
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signal sResetStage1 : std_logic;
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signal sResetStage1 : std_logic;
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begin
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begin
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process(iClk, iAsyncReset)
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process(iClk, iAsyncReset)
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begin
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begin
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if iAsyncReset = '1' then
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if iAsyncReset = '1' then
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sResetStage1 <= '1';
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sResetStage1 <= '1';
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oSyncReset <= '1';
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oSyncReset <= '1';
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elsif rising_edge(iClk) then
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elsif rising_edge(iClk) then
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sResetStage1 <= '0';
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sResetStage1 <= '0';
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oSyncReset <= sResetStage1;
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oSyncReset <= sResetStage1;
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end if;
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end if;
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end process;
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end process;
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end SyncReset;
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end SyncReset;
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