---------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Copyright (c) 2013 VariStream
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-- --
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-- Author : Yu Peng
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-- Copyright (C) 2013 Author and VariStream Studio --
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-- Author : Yu Peng --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer. --
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-- --
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-- This source file is free software; you can redistribute it --
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-- and/or modify it under the terms of the GNU Lesser General --
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-- Public License as published by the Free Software Foundation; --
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-- either version 2.1 of the License, or (at your option) any --
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-- later version. --
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-- --
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-- This source is distributed in the hope that it will be --
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-- useful, but WITHOUT ANY WARRANTY; without even the implied --
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
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-- PURPOSE. See the GNU Lesser General Public License for more --
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-- details. --
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-- --
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-- You should have received a copy of the GNU Lesser General --
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-- Public License along with this source; if not, download it --
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-- from http://www.opencores.org/lgpl.shtml --
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-- --
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-------------------------------------------------------------------
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-- Description:
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-- Description:
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-- Implement BRAM according to gADDRESS_WIDTH and gDATA_WIDTH
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-- Implement BRAM according to gADDRESS_WIDTH and gDATA_WIDTH
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-- Maxim number of data word is (2**gADDRESS_WIDTH - 1)
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-- Maxim number of data word is (2**gADDRESS_WIDTH - 1)
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---------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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--use synplify.attributes.all;
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--use synplify.attributes.all;
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entity sync_fifo_infer is
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entity sync_fifo_infer is
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generic (
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generic (
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gADDRESS_WIDTH : integer range 4 to (integer'HIGH) := 8;
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gADDRESS_WIDTH : integer range 4 to (integer'HIGH) := 8;
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gDATA_WIDTH : integer := 32;
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gDATA_WIDTH : integer := 32;
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gDYNAMIC_PROG_FULL_TH : boolean := false;
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gDYNAMIC_PROG_FULL_TH : boolean := false;
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gDYNAMIC_PROG_EMPTY_TH : boolean := false;
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gDYNAMIC_PROG_EMPTY_TH : boolean := false;
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gOUTPUT_PIPELINE_NUM : integer range 1 to (integer'HIGH) := 1
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gOUTPUT_PIPELINE_NUM : integer range 1 to (integer'HIGH) := 1
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);
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);
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port(
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port(
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iClk : in std_logic := '0';
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iClk : in std_logic := '0';
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iReset_sync : in std_logic := '0';
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iReset_sync : in std_logic := '0';
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ivProgFullTh : in std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2**gADDRESS_WIDTH-3, gADDRESS_WIDTH);
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ivProgFullTh : in std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2**gADDRESS_WIDTH-3, gADDRESS_WIDTH);
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ivProgEmptyTh : in std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2, gADDRESS_WIDTH);
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ivProgEmptyTh : in std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2, gADDRESS_WIDTH);
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iWrEn : in std_logic := '0';
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iWrEn : in std_logic := '0';
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iRdEn : in std_logic := '0';
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iRdEn : in std_logic := '0';
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ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
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ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
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ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
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ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
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oDataOutValid : out std_logic := '0';
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oDataOutValid : out std_logic := '0';
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oFull : out std_logic := '0';
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oFull : out std_logic := '0';
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oEmpty : out std_logic := '1';
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oEmpty : out std_logic := '1';
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oAlmostFull : out std_logic := '0';
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oAlmostFull : out std_logic := '0';
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oAlmostEmpty : out std_logic := '1';
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oAlmostEmpty : out std_logic := '1';
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oProgFull : out std_logic := '0';
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oProgFull : out std_logic := '0';
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oProgEmpty : out std_logic := '1';
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oProgEmpty : out std_logic := '1';
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oOverflow : out std_logic := '0';
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oOverflow : out std_logic := '0';
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oUnderflow : out std_logic := '0'
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oUnderflow : out std_logic := '0'
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);
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);
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end sync_fifo_infer;
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end sync_fifo_infer;
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ARCHITECTURE behavioral OF sync_fifo_infer IS
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ARCHITECTURE behavioral OF sync_fifo_infer IS
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component sdpram_infer_read_first_outreg is
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component sdpram_infer_read_first_outreg is
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generic (
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generic (
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gADDRESS_WIDTH : integer := 5;
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gADDRESS_WIDTH : integer := 5;
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gDATA_WIDTH : integer := 24
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gDATA_WIDTH : integer := 24
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);
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);
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port (
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port (
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iClk : in std_logic;
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iClk : in std_logic;
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iReset_sync : in std_logic;
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iReset_sync : in std_logic;
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iWe : in std_logic;
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iWe : in std_logic;
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ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
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ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
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ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
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ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
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ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);
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ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);
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ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)
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ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)
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);
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);
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end component;
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end component;
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component sdpram_infer_read_first_outreset is
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component sdpram_infer_read_first_outreset is
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generic (
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generic (
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gADDRESS_WIDTH : integer := 5;
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gADDRESS_WIDTH : integer := 5;
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gDATA_WIDTH : integer := 24
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gDATA_WIDTH : integer := 24
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);
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);
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port (
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port (
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iClk : in std_logic;
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iClk : in std_logic;
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iReset_sync : in std_logic;
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iReset_sync : in std_logic;
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iWe : in std_logic;
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iWe : in std_logic;
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ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
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ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
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ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
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ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
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ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);
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ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);
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ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)
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ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)
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);
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);
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end component;
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end component;
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component pipelines_without_reset IS
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component pipelines_without_reset IS
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GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);
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GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);
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PORT(
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PORT(
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iClk : IN STD_LOGIC;
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iClk : IN STD_LOGIC;
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iInput : IN STD_LOGIC;
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iInput : IN STD_LOGIC;
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ivInput : IN STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0);
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ivInput : IN STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0);
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oDelayed_output : OUT STD_LOGIC;
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oDelayed_output : OUT STD_LOGIC;
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ovDelayed_output : OUT STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0)
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ovDelayed_output : OUT STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0)
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);
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);
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END component;
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END component;
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signal svWriteAddr : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');
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signal svWriteAddr : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');
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signal svReadAddr : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');
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signal svReadAddr : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');
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signal sEffectiveWrEn : std_logic := '0';
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signal sEffectiveWrEn : std_logic := '0';
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signal sEffectiveRdEn : std_logic := '0';
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signal sEffectiveRdEn : std_logic := '0';
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signal svFifoCount : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');
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signal svFifoCount : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');
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signal svProgFullThM1 : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2**gADDRESS_WIDTH-4, gADDRESS_WIDTH);
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signal svProgFullThM1 : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2**gADDRESS_WIDTH-4, gADDRESS_WIDTH);
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signal svProgEmptyThP1 : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(3, gADDRESS_WIDTH);
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signal svProgEmptyThP1 : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(3, gADDRESS_WIDTH);
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signal sFifoFull : std_logic := '0';
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signal sFifoFull : std_logic := '0';
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signal sFifoEmpty : std_logic := '1';
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signal sFifoEmpty : std_logic := '1';
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signal sAlmostFull : std_logic := '0';
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signal sAlmostFull : std_logic := '0';
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signal sAlmostEmpty : std_logic := '1';
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signal sAlmostEmpty : std_logic := '1';
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signal sProgFull : std_logic := '0';
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signal sProgFull : std_logic := '0';
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signal sProgEmpty : std_logic := '1';
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signal sProgEmpty : std_logic := '1';
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signal sFifoOverflow : std_logic := '0';
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signal sFifoOverflow : std_logic := '0';
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signal sFifoUnderflow : std_logic := '0';
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signal sFifoUnderflow : std_logic := '0';
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signal svMemDataOut : std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
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signal svMemDataOut : std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
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signal sMemDataOutValid : std_logic := '0';
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signal sMemDataOutValid : std_logic := '0';
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signal svPipeDataOut : std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
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signal svPipeDataOut : std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
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signal sPipeDataOutValid: std_logic := '0';
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signal sPipeDataOutValid: std_logic := '0';
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BEGIN
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BEGIN
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sdpram_gen_1: if gOUTPUT_PIPELINE_NUM = 1 generate
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sdpram_gen_1: if gOUTPUT_PIPELINE_NUM = 1 generate
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sdpram_inst: sdpram_infer_read_first_outreset
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sdpram_inst: sdpram_infer_read_first_outreset
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generic map(
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generic map(
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gADDRESS_WIDTH => gADDRESS_WIDTH,
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gADDRESS_WIDTH => gADDRESS_WIDTH,
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gDATA_WIDTH => gDATA_WIDTH
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gDATA_WIDTH => gDATA_WIDTH
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)
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)
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port map(
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port map(
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iClk => iClk,
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iClk => iClk,
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iReset_sync => iReset_sync,
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iReset_sync => iReset_sync,
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iWe => iWrEn,
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iWe => iWrEn,
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ivWrAddr => svWriteAddr,
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ivWrAddr => svWriteAddr,
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ivRdAddr => svReadAddr,
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ivRdAddr => svReadAddr,
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ivDataIn => ivDataIn,
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ivDataIn => ivDataIn,
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ovDataOut => svMemDataOut
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ovDataOut => svMemDataOut
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);
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);
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process(iClk)
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process(iClk)
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begin
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begin
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if rising_edge(iClk) then
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if rising_edge(iClk) then
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if iReset_sync = '1' then
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if iReset_sync = '1' then
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sMemDataOutValid <= '0';
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sMemDataOutValid <= '0';
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else
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else
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sMemDataOutValid <= iRdEn;
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sMemDataOutValid <= iRdEn;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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sdpram_gen_others: if gOUTPUT_PIPELINE_NUM > 1 generate
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sdpram_gen_others: if gOUTPUT_PIPELINE_NUM > 1 generate
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sdpram_inst: sdpram_infer_read_first_outreg
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sdpram_inst: sdpram_infer_read_first_outreg
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generic map(
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generic map(
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gADDRESS_WIDTH => gADDRESS_WIDTH,
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gADDRESS_WIDTH => gADDRESS_WIDTH,
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gDATA_WIDTH => gDATA_WIDTH
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gDATA_WIDTH => gDATA_WIDTH
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)
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)
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port map(
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port map(
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iClk => iClk,
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iClk => iClk,
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iReset_sync => iReset_sync,
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iReset_sync => iReset_sync,
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iWe => iWrEn,
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iWe => iWrEn,
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ivWrAddr => svWriteAddr,
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ivWrAddr => svWriteAddr,
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ivRdAddr => svReadAddr,
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ivRdAddr => svReadAddr,
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ivDataIn => ivDataIn,
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ivDataIn => ivDataIn,
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ovDataOut => svMemDataOut
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ovDataOut => svMemDataOut
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);
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);
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process(iClk)
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process(iClk)
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begin
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begin
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if rising_edge(iClk) then
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if rising_edge(iClk) then
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sMemDataOutValid <= iRdEn;
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sMemDataOutValid <= iRdEn;
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Generate the write and read pointers
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-- Generate the write and read pointers
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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process(iClk)
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process(iClk)
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begin
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begin
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if rising_edge(iClk) then
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if rising_edge(iClk) then
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if iReset_sync = '1' then
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if iReset_sync = '1' then
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svWriteAddr <= (others=>'0');
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svWriteAddr <= (others=>'0');
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elsif sEffectiveWrEn = '1' then
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elsif sEffectiveWrEn = '1' then
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svWriteAddr <= svWriteAddr + '1';
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svWriteAddr <= svWriteAddr + '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process(iClk)
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process(iClk)
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begin
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begin
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if rising_edge(iClk) then
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if rising_edge(iClk) then
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if iReset_sync = '1' then
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if iReset_sync = '1' then
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svReadAddr <= (others=>'0');
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svReadAddr <= (others=>'0');
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elsif sEffectiveRdEn = '1' then
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elsif sEffectiveRdEn = '1' then
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svReadAddr <= svReadAddr + '1';
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svReadAddr <= svReadAddr + '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Generate Fifo Flags
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-- Generate Fifo Flags
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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sEffectiveWrEn <= iWrEn and (not sFifoFull);
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sEffectiveWrEn <= iWrEn and (not sFifoFull);
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sEffectiveRdEn <= iRdEn and (not sFifoEmpty);
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sEffectiveRdEn <= iRdEn and (not sFifoEmpty);
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ProgFullThM1_gen_dynamic : if gDYNAMIC_PROG_FULL_TH = true generate
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ProgFullThM1_gen_dynamic : if gDYNAMIC_PROG_FULL_TH = true generate
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process (iClk)
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process (iClk)
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begin
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begin
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if rising_edge(iClk) then
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if rising_edge(iClk) then
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svProgFullThM1 <= ivProgFullTh - '1';
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svProgFullThM1 <= ivProgFullTh - '1';
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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ProgFullThM1_gen_static : if gDYNAMIC_PROG_FULL_TH = false generate
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ProgFullThM1_gen_static : if gDYNAMIC_PROG_FULL_TH = false generate
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svProgFullThM1 <= ivProgFullTh - '1';
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svProgFullThM1 <= ivProgFullTh - '1';
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end generate;
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end generate;
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ProgEmptyThM1_gen_dynamic : if gDYNAMIC_PROG_EMPTY_TH = true generate
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ProgEmptyThM1_gen_dynamic : if gDYNAMIC_PROG_EMPTY_TH = true generate
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process (iClk)
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process (iClk)
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begin
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begin
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if rising_edge(iClk) then
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if rising_edge(iClk) then
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svProgEmptyThP1 <= ivProgEmptyTh + '1';
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svProgEmptyThP1 <= ivProgEmptyTh + '1';
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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ProgEmptyThM1_gen_static : if gDYNAMIC_PROG_EMPTY_TH = false generate
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ProgEmptyThM1_gen_static : if gDYNAMIC_PROG_EMPTY_TH = false generate
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svProgEmptyThP1 <= ivProgEmptyTh + '1';
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svProgEmptyThP1 <= ivProgEmptyTh + '1';
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end generate;
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end generate;
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process (iClk)
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process (iClk)
|
begin
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begin
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if rising_edge(iClk) then
|
if rising_edge(iClk) then
|
if (iReset_sync = '1') then
|
if (iReset_sync = '1') then
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svFifoCount <= (others => '0');
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svFifoCount <= (others => '0');
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sFifoFull <= '0';
|
sFifoFull <= '0';
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sFifoEmpty <= '1';
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sFifoEmpty <= '1';
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sAlmostFull <= '0';
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sAlmostFull <= '0';
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sAlmostEmpty <= '1';
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sAlmostEmpty <= '1';
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sProgFull <= '0';
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sProgFull <= '0';
|
sProgEmpty <= '1';
|
sProgEmpty <= '1';
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|
|
sFifoOverflow <= '0';
|
sFifoOverflow <= '0';
|
sFifoUnderflow <= '0';
|
sFifoUnderflow <= '0';
|
else
|
else
|
-- Fifo count when it is read or written
|
-- Fifo count when it is read or written
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if (sEffectiveWrEn = '1') and (sEffectiveRdEn = '0') then
|
if (sEffectiveWrEn = '1') and (sEffectiveRdEn = '0') then
|
svFifoCount <= svFifoCount + '1';
|
svFifoCount <= svFifoCount + '1';
|
elsif (sEffectiveWrEn = '0') and (sEffectiveRdEn = '1') then
|
elsif (sEffectiveWrEn = '0') and (sEffectiveRdEn = '1') then
|
svFifoCount <= svFifoCount - '1';
|
svFifoCount <= svFifoCount - '1';
|
end if;
|
end if;
|
|
|
if svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-2, gADDRESS_WIDTH) then
|
if svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-2, gADDRESS_WIDTH) then
|
if (iWrEn = '1') and (iRdEn = '0') then
|
if (iWrEn = '1') and (iRdEn = '0') then
|
sFifoFull <= '1';
|
sFifoFull <= '1';
|
else
|
else
|
sFifoFull <= '0';
|
sFifoFull <= '0';
|
end if;
|
end if;
|
elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-1, gADDRESS_WIDTH) then
|
elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-1, gADDRESS_WIDTH) then
|
if iRdEn = '1' then
|
if iRdEn = '1' then
|
sFifoFull <= '0';
|
sFifoFull <= '0';
|
else
|
else
|
sFifoFull <= '1';
|
sFifoFull <= '1';
|
end if;
|
end if;
|
else
|
else
|
sFifoFull <= '0';
|
sFifoFull <= '0';
|
end if;
|
end if;
|
|
|
if svFifoCount = conv_std_logic_vector(1, gADDRESS_WIDTH) then
|
if svFifoCount = conv_std_logic_vector(1, gADDRESS_WIDTH) then
|
if (iWrEn = '0') and (iRdEn = '1') then
|
if (iWrEn = '0') and (iRdEn = '1') then
|
sFifoEmpty <= '1';
|
sFifoEmpty <= '1';
|
else
|
else
|
sFifoEmpty <= '0';
|
sFifoEmpty <= '0';
|
end if;
|
end if;
|
elsif svFifoCount = conv_std_logic_vector(0, gADDRESS_WIDTH) then
|
elsif svFifoCount = conv_std_logic_vector(0, gADDRESS_WIDTH) then
|
if (iWrEn = '1') then
|
if (iWrEn = '1') then
|
sFifoEmpty <= '0';
|
sFifoEmpty <= '0';
|
else
|
else
|
sFifoEmpty <= '1';
|
sFifoEmpty <= '1';
|
end if;
|
end if;
|
else
|
else
|
sFifoEmpty <= '0';
|
sFifoEmpty <= '0';
|
end if;
|
end if;
|
|
|
if svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-3, gADDRESS_WIDTH) then
|
if svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-3, gADDRESS_WIDTH) then
|
if (iWrEn = '1') and (iRdEn = '0') then
|
if (iWrEn = '1') and (iRdEn = '0') then
|
sAlmostFull <= '1';
|
sAlmostFull <= '1';
|
else
|
else
|
sAlmostFull <= '0';
|
sAlmostFull <= '0';
|
end if;
|
end if;
|
elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-2, gADDRESS_WIDTH) then
|
elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-2, gADDRESS_WIDTH) then
|
if (iWrEn = '0') and (iRdEn = '1') then
|
if (iWrEn = '0') and (iRdEn = '1') then
|
sAlmostFull <= '0';
|
sAlmostFull <= '0';
|
else
|
else
|
sAlmostFull <= '1';
|
sAlmostFull <= '1';
|
end if;
|
end if;
|
elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-1, gADDRESS_WIDTH) then
|
elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-1, gADDRESS_WIDTH) then
|
sAlmostFull <= '1';
|
sAlmostFull <= '1';
|
else
|
else
|
sAlmostFull <= '0';
|
sAlmostFull <= '0';
|
end if;
|
end if;
|
|
|
if svFifoCount = conv_std_logic_vector(2, gADDRESS_WIDTH) then
|
if svFifoCount = conv_std_logic_vector(2, gADDRESS_WIDTH) then
|
if (iWrEn = '0') and (iRdEn = '1') then
|
if (iWrEn = '0') and (iRdEn = '1') then
|
sAlmostEmpty <= '1';
|
sAlmostEmpty <= '1';
|
else
|
else
|
sAlmostEmpty <= '0';
|
sAlmostEmpty <= '0';
|
end if;
|
end if;
|
elsif svFifoCount = conv_std_logic_vector(1, gADDRESS_WIDTH) then
|
elsif svFifoCount = conv_std_logic_vector(1, gADDRESS_WIDTH) then
|
if (iWrEn = '1') and (iRdEn = '0') then
|
if (iWrEn = '1') and (iRdEn = '0') then
|
sAlmostEmpty <= '0';
|
sAlmostEmpty <= '0';
|
else
|
else
|
sAlmostEmpty <= '1';
|
sAlmostEmpty <= '1';
|
end if;
|
end if;
|
elsif svFifoCount = conv_std_logic_vector(0, gADDRESS_WIDTH) then
|
elsif svFifoCount = conv_std_logic_vector(0, gADDRESS_WIDTH) then
|
sAlmostEmpty <= '1';
|
sAlmostEmpty <= '1';
|
else
|
else
|
sAlmostEmpty <= '0';
|
sAlmostEmpty <= '0';
|
end if;
|
end if;
|
|
|
if svFifoCount = svProgFullThM1 then
|
if svFifoCount = svProgFullThM1 then
|
if (iWrEn = '1') and (iRdEn = '0') then
|
if (iWrEn = '1') and (iRdEn = '0') then
|
sProgFull <= '1';
|
sProgFull <= '1';
|
else
|
else
|
sProgFull <= '0';
|
sProgFull <= '0';
|
end if;
|
end if;
|
elsif svFifoCount = ivProgFullTh then
|
elsif svFifoCount = ivProgFullTh then
|
if (iWrEn = '0') and (iRdEn = '1') then
|
if (iWrEn = '0') and (iRdEn = '1') then
|
sProgFull <= '0';
|
sProgFull <= '0';
|
else
|
else
|
sProgFull <= '1';
|
sProgFull <= '1';
|
end if;
|
end if;
|
elsif svFifoCount > ivProgFullTh then
|
elsif svFifoCount > ivProgFullTh then
|
sProgFull <= '1';
|
sProgFull <= '1';
|
else
|
else
|
sProgFull <= '0';
|
sProgFull <= '0';
|
end if;
|
end if;
|
|
|
if svFifoCount = svProgEmptyThP1 then
|
if svFifoCount = svProgEmptyThP1 then
|
if (iWrEn = '0') and (iRdEn = '1') then
|
if (iWrEn = '0') and (iRdEn = '1') then
|
sProgEmpty <= '1';
|
sProgEmpty <= '1';
|
else
|
else
|
sProgEmpty <= '0';
|
sProgEmpty <= '0';
|
end if;
|
end if;
|
elsif svFifoCount = ivProgEmptyTh then
|
elsif svFifoCount = ivProgEmptyTh then
|
if (iWrEn = '1') and (iRdEn = '0') then
|
if (iWrEn = '1') and (iRdEn = '0') then
|
sProgEmpty <= '0';
|
sProgEmpty <= '0';
|
else
|
else
|
sProgEmpty <= '1';
|
sProgEmpty <= '1';
|
end if;
|
end if;
|
elsif svFifoCount < ivProgEmptyTh then
|
elsif svFifoCount < ivProgEmptyTh then
|
sProgEmpty <= '1';
|
sProgEmpty <= '1';
|
else
|
else
|
sProgEmpty <= '0';
|
sProgEmpty <= '0';
|
end if;
|
end if;
|
--------------------------------
|
--------------------------------
|
-- Generate the error flag
|
-- Generate the error flag
|
-------------------------------
|
-------------------------------
|
if sFifoFull = '1' and iWrEn = '1' then
|
if sFifoFull = '1' and iWrEn = '1' then
|
sFifoOverflow <= '1';
|
sFifoOverflow <= '1';
|
end if;
|
end if;
|
|
|
if sFifoEmpty = '1' and iRdEn = '1' then
|
if sFifoEmpty = '1' and iRdEn = '1' then
|
sFifoUnderflow <= '1';
|
sFifoUnderflow <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
oFull <= sFifoFull;
|
oFull <= sFifoFull;
|
oEmpty <= sFifoEmpty;
|
oEmpty <= sFifoEmpty;
|
oAlmostFull <= sAlmostFull;
|
oAlmostFull <= sAlmostFull;
|
oAlmostEmpty <= sAlmostEmpty;
|
oAlmostEmpty <= sAlmostEmpty;
|
oProgFull <= sProgFull;
|
oProgFull <= sProgFull;
|
oProgEmpty <= sProgEmpty;
|
oProgEmpty <= sProgEmpty;
|
oOverflow <= sFifoOverflow;
|
oOverflow <= sFifoOverflow;
|
oUnderflow <= sFifoUnderflow;
|
oUnderflow <= sFifoUnderflow;
|
|
|
-------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------
|
-- This section generates the code for the output pipelines
|
-- This section generates the code for the output pipelines
|
-------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------
|
OutputPipeline_gen_1: if gOUTPUT_PIPELINE_NUM = 1 generate
|
OutputPipeline_gen_1: if gOUTPUT_PIPELINE_NUM = 1 generate
|
ovDataOut <= svMemDataOut;
|
ovDataOut <= svMemDataOut;
|
oDataOutValid <= sMemDataOutValid;
|
oDataOutValid <= sMemDataOutValid;
|
end generate;
|
end generate;
|
|
|
OutputPipeline_gen_2: if gOUTPUT_PIPELINE_NUM = 2 generate
|
OutputPipeline_gen_2: if gOUTPUT_PIPELINE_NUM = 2 generate
|
process (iClk)
|
process (iClk)
|
begin
|
begin
|
if rising_edge(iClk) then
|
if rising_edge(iClk) then
|
if (iReset_sync = '1') then
|
if (iReset_sync = '1') then
|
ovDataOut <= (others=>'0');
|
ovDataOut <= (others=>'0');
|
oDataOutValid <= '0';
|
oDataOutValid <= '0';
|
else
|
else
|
ovDataOut <= svMemDataOut;
|
ovDataOut <= svMemDataOut;
|
oDataOutValid <= sMemDataOutValid;
|
oDataOutValid <= sMemDataOutValid;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
end generate;
|
end generate;
|
|
|
OutputPipeline_gen_others: if gOUTPUT_PIPELINE_NUM > 2 generate
|
OutputPipeline_gen_others: if gOUTPUT_PIPELINE_NUM > 2 generate
|
pipelines_without_reset_inst_output: pipelines_without_reset
|
pipelines_without_reset_inst_output: pipelines_without_reset
|
GENERIC map(
|
GENERIC map(
|
gBUS_WIDTH => gDATA_WIDTH,
|
gBUS_WIDTH => gDATA_WIDTH,
|
gNB_PIPELINES => (gOUTPUT_PIPELINE_NUM-1)
|
gNB_PIPELINES => (gOUTPUT_PIPELINE_NUM-1)
|
)
|
)
|
PORT map(
|
PORT map(
|
iClk => iClk,
|
iClk => iClk,
|
iInput => sMemDataOutValid,
|
iInput => sMemDataOutValid,
|
ivInput => svMemDataOut,
|
ivInput => svMemDataOut,
|
oDelayed_output => sPipeDataOutValid,
|
oDelayed_output => sPipeDataOutValid,
|
ovDelayed_output => svPipeDataOut
|
ovDelayed_output => svPipeDataOut
|
);
|
);
|
|
|
process (iClk)
|
process (iClk)
|
begin
|
begin
|
if rising_edge(iClk) then
|
if rising_edge(iClk) then
|
if (iReset_sync = '1') then
|
if (iReset_sync = '1') then
|
ovDataOut <= (others=>'0');
|
ovDataOut <= (others=>'0');
|
oDataOutValid <= '0';
|
oDataOutValid <= '0';
|
else
|
else
|
ovDataOut <= svPipeDataOut;
|
ovDataOut <= svPipeDataOut;
|
oDataOutValid <= sPipeDataOutValid;
|
oDataOutValid <= sPipeDataOutValid;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
end generate;
|
end generate;
|
|
|
END behavioral;
|
END behavioral;
|
|
|
|
|
|
|
|
|
