-- Copyright (c) 2013 VariStream
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-------------------------------------------------------------------
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-- Author : Yu Peng
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-- --
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-- Copyright (C) 2013 Author and VariStream Studio --
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-- Author : Yu Peng --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer. --
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-- --
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-- This source file is free software; you can redistribute it --
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-- and/or modify it under the terms of the GNU Lesser General --
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-- Public License as published by the Free Software Foundation; --
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-- either version 2.1 of the License, or (at your option) any --
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-- later version. --
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-- --
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-- This source is distributed in the hope that it will be --
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-- useful, but WITHOUT ANY WARRANTY; without even the implied --
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
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-- PURPOSE. See the GNU Lesser General Public License for more --
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-- details. --
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-- --
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-- You should have received a copy of the GNU Lesser General --
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-- Public License along with this source; if not, download it --
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-- from http://www.opencores.org/lgpl.shtml --
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-- --
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-------------------------------------------------------------------
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-- Notes : Introduce delay of 1 clock cycle
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-- Notes : Introduce delay of 1 clock cycle
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-------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.sha_256_pkg.ALL;
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use work.sha_256_pkg.ALL;
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entity sha_256_ext_func_1c is
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entity sha_256_ext_func_1c is
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port(
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port(
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iClk : in std_logic;
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iClk : in std_logic;
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iRst_async : in std_logic;
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iRst_async : in std_logic;
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ivWIM2 : in std_logic_vector(31 downto 0);
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ivWIM2 : in std_logic_vector(31 downto 0);
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ivWIM7 : in std_logic_vector(31 downto 0);
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ivWIM7 : in std_logic_vector(31 downto 0);
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ivWIM15 : in std_logic_vector(31 downto 0);
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ivWIM15 : in std_logic_vector(31 downto 0);
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ivWIM16 : in std_logic_vector(31 downto 0);
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ivWIM16 : in std_logic_vector(31 downto 0);
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ovWO : out std_logic_vector(31 downto 0)
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ovWO : out std_logic_vector(31 downto 0)
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);
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);
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end sha_256_ext_func_1c;
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end sha_256_ext_func_1c;
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architecture behavioral of sha_256_ext_func_1c is
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architecture behavioral of sha_256_ext_func_1c is
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begin
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begin
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process(iClk)
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process(iClk)
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begin
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begin
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if rising_edge(iClk) then
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if rising_edge(iClk) then
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ovWO <= ivWIM16 + sigma_0(ivWIM15) + ivWIM7 + sigma_1(ivWIM2);
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ovWO <= ivWIM16 + sigma_0(ivWIM15) + ivWIM7 + sigma_1(ivWIM2);
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end if;
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end if;
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end process;
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end process;
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end behavioral;
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end behavioral;
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