/*******************************************************************************
|
/*******************************************************************************
|
* This file is owned and controlled by Xilinx and must be used *
|
* This file is owned and controlled by Xilinx and must be used *
|
* solely for design, simulation, implementation and creation of *
|
* solely for design, simulation, implementation and creation of *
|
* design files limited to Xilinx devices or technologies. Use *
|
* design files limited to Xilinx devices or technologies. Use *
|
* with non-Xilinx devices or technologies is expressly prohibited *
|
* with non-Xilinx devices or technologies is expressly prohibited *
|
* and immediately terminates your license. *
|
* and immediately terminates your license. *
|
* *
|
* *
|
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
* FOR A PARTICULAR PURPOSE. *
|
* FOR A PARTICULAR PURPOSE. *
|
* *
|
* *
|
* Xilinx products are not intended for use in life support *
|
* Xilinx products are not intended for use in life support *
|
* appliances, devices, or systems. Use in such applications are *
|
* appliances, devices, or systems. Use in such applications are *
|
* expressly prohibited. *
|
* expressly prohibited. *
|
* *
|
* *
|
* (c) Copyright 1995-2007 Xilinx, Inc. *
|
* (c) Copyright 1995-2007 Xilinx, Inc. *
|
* All rights reserved. *
|
* All rights reserved. *
|
*******************************************************************************/
|
*******************************************************************************/
|
// The synthesis directives "translate_off/translate_on" specified below are
|
// The synthesis directives "translate_off/translate_on" specified below are
|
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
|
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
|
// tools. Ensure they are correct for your synthesis tool(s).
|
// tools. Ensure they are correct for your synthesis tool(s).
|
|
|
// You must compile the wrapper file blk_mem_gen_v2_7.v when simulating
|
// You must compile the wrapper file blk_mem_gen_v2_7.v when simulating
|
// the core, blk_mem_gen_v2_7. When compiling the wrapper file, be sure to
|
// the core, blk_mem_gen_v2_7. When compiling the wrapper file, be sure to
|
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
// instructions, please refer to the "CORE Generator Help".
|
// instructions, please refer to the "CORE Generator Help".
|
|
|
`timescale 1ns/1ps
|
`timescale 1ns/1ps
|
|
|
module blk_mem_gen_v2_7(
|
module blk_mem_gen_v2_7(
|
clka,
|
clka,
|
dina,
|
dina,
|
addra,
|
addra,
|
ena,
|
ena,
|
wea,
|
wea,
|
douta,
|
douta,
|
clkb,
|
clkb,
|
dinb,
|
dinb,
|
addrb,
|
addrb,
|
enb,
|
enb,
|
web,
|
web,
|
doutb);
|
doutb);
|
|
|
|
|
input clka;
|
input clka;
|
input [15 : 0] dina;
|
input [15 : 0] dina;
|
input [15 : 0] addra;
|
input [15 : 0] addra;
|
input ena;
|
input ena;
|
input [0 : 0] wea;
|
input [0 : 0] wea;
|
output [15 : 0] douta;
|
output [15 : 0] douta;
|
input clkb;
|
input clkb;
|
input [15 : 0] dinb;
|
input [15 : 0] dinb;
|
input [15 : 0] addrb;
|
input [15 : 0] addrb;
|
input enb;
|
input enb;
|
input [0 : 0] web;
|
input [0 : 0] web;
|
output [15 : 0] doutb;
|
output [15 : 0] doutb;
|
|
|
// synthesis translate_off
|
// synthesis translate_off
|
|
|
BLK_MEM_GEN_V2_7 #(
|
BLK_MEM_GEN_V2_7 #(
|
.C_ADDRA_WIDTH(16),
|
.C_ADDRA_WIDTH(16),
|
.C_ADDRB_WIDTH(16),
|
.C_ADDRB_WIDTH(16),
|
.C_ALGORITHM(1),
|
.C_ALGORITHM(1),
|
.C_BYTE_SIZE(9),
|
.C_BYTE_SIZE(9),
|
.C_COMMON_CLK(0),
|
.C_COMMON_CLK(0),
|
.C_DEFAULT_DATA("0"),
|
.C_DEFAULT_DATA("0"),
|
.C_DISABLE_WARN_BHV_COLL(0),
|
.C_DISABLE_WARN_BHV_COLL(0),
|
.C_DISABLE_WARN_BHV_RANGE(0),
|
.C_DISABLE_WARN_BHV_RANGE(0),
|
.C_FAMILY("spartan3"),
|
.C_FAMILY("spartan3"),
|
.C_HAS_ENA(1),
|
.C_HAS_ENA(1),
|
.C_HAS_ENB(1),
|
.C_HAS_ENB(1),
|
.C_HAS_MEM_OUTPUT_REGS_A(0),
|
.C_HAS_MEM_OUTPUT_REGS_A(0),
|
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
.C_HAS_MUX_OUTPUT_REGS_A(0),
|
.C_HAS_MUX_OUTPUT_REGS_A(0),
|
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
.C_HAS_REGCEA(0),
|
.C_HAS_REGCEA(0),
|
.C_HAS_REGCEB(0),
|
.C_HAS_REGCEB(0),
|
.C_HAS_SSRA(0),
|
.C_HAS_SSRA(0),
|
.C_HAS_SSRB(0),
|
.C_HAS_SSRB(0),
|
.C_INIT_FILE_NAME("blk_mem_gen_v2_7.mif"),
|
.C_INIT_FILE_NAME("blk_mem_gen_v2_7.mif"),
|
.C_LOAD_INIT_FILE(1),
|
.C_LOAD_INIT_FILE(1),
|
.C_MEM_TYPE(2),
|
.C_MEM_TYPE(2),
|
.C_MUX_PIPELINE_STAGES(0),
|
.C_MUX_PIPELINE_STAGES(0),
|
.C_PRIM_TYPE(1),
|
.C_PRIM_TYPE(1),
|
.C_READ_DEPTH_A(40000),
|
.C_READ_DEPTH_A(40000),
|
.C_READ_DEPTH_B(40000),
|
.C_READ_DEPTH_B(40000),
|
.C_READ_WIDTH_A(16),
|
.C_READ_WIDTH_A(16),
|
.C_READ_WIDTH_B(16),
|
.C_READ_WIDTH_B(16),
|
.C_SIM_COLLISION_CHECK("ALL"),
|
.C_SIM_COLLISION_CHECK("ALL"),
|
.C_SINITA_VAL("0"),
|
.C_SINITA_VAL("0"),
|
.C_SINITB_VAL("0"),
|
.C_SINITB_VAL("0"),
|
.C_USE_BYTE_WEA(0),
|
.C_USE_BYTE_WEA(0),
|
.C_USE_BYTE_WEB(0),
|
.C_USE_BYTE_WEB(0),
|
.C_USE_DEFAULT_DATA(0),
|
.C_USE_DEFAULT_DATA(0),
|
.C_USE_ECC(0),
|
.C_USE_ECC(0),
|
.C_USE_RAMB16BWER_RST_BHV(0),
|
.C_USE_RAMB16BWER_RST_BHV(0),
|
.C_WEA_WIDTH(1),
|
.C_WEA_WIDTH(1),
|
.C_WEB_WIDTH(1),
|
.C_WEB_WIDTH(1),
|
.C_WRITE_DEPTH_A(40000),
|
.C_WRITE_DEPTH_A(40000),
|
.C_WRITE_DEPTH_B(40000),
|
.C_WRITE_DEPTH_B(40000),
|
.C_WRITE_MODE_A("WRITE_FIRST"),
|
.C_WRITE_MODE_A("WRITE_FIRST"),
|
.C_WRITE_MODE_B("WRITE_FIRST"),
|
.C_WRITE_MODE_B("WRITE_FIRST"),
|
.C_WRITE_WIDTH_A(16),
|
.C_WRITE_WIDTH_A(16),
|
.C_WRITE_WIDTH_B(16),
|
.C_WRITE_WIDTH_B(16),
|
.C_XDEVICEFAMILY("spartan3"))
|
.C_XDEVICEFAMILY("spartan3"))
|
inst (
|
inst (
|
.CLKA(clka),
|
.CLKA(clka),
|
.DINA(dina),
|
.DINA(dina),
|
.ADDRA(addra),
|
.ADDRA(addra),
|
.ENA(ena),
|
.ENA(ena),
|
.WEA(wea),
|
.WEA(wea),
|
.DOUTA(douta),
|
.DOUTA(douta),
|
.CLKB(clkb),
|
.CLKB(clkb),
|
.DINB(dinb),
|
.DINB(dinb),
|
.ADDRB(addrb),
|
.ADDRB(addrb),
|
.ENB(enb),
|
.ENB(enb),
|
.WEB(web),
|
.WEB(web),
|
.DOUTB(doutb),
|
.DOUTB(doutb),
|
.REGCEA(),
|
.REGCEA(),
|
.SSRA(),
|
.SSRA(),
|
.REGCEB(),
|
.REGCEB(),
|
.SSRB(),
|
.SSRB(),
|
.DBITERR(),
|
.DBITERR(),
|
.SBITERR());
|
.SBITERR());
|
|
|
|
|
// synthesis translate_on
|
// synthesis translate_on
|
|
|
endmodule
|
endmodule
|
|
|
|
|