Release 10.1 - xst K.31 (nt)
|
Release 10.1 - xst K.31 (nt)
|
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
|
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
|
--> Parameter TMPDIR set to X:/Display_Controller/xst/projnav.tmp
|
--> Parameter TMPDIR set to X:/Display_Controller/xst/projnav.tmp
|
|
|
|
|
Total REAL time to Xst completion: 0.00 secs
|
Total REAL time to Xst completion: 0.00 secs
|
Total CPU time to Xst completion: 0.20 secs
|
Total CPU time to Xst completion: 0.20 secs
|
|
|
--> Parameter xsthdpdir set to X:/Display_Controller/xst
|
--> Parameter xsthdpdir set to X:/Display_Controller/xst
|
|
|
|
|
Total REAL time to Xst completion: 0.00 secs
|
Total REAL time to Xst completion: 0.00 secs
|
Total CPU time to Xst completion: 0.20 secs
|
Total CPU time to Xst completion: 0.20 secs
|
|
|
--> Reading design: Display_Controller.prj
|
--> Reading design: Display_Controller.prj
|
|
|
TABLE OF CONTENTS
|
TABLE OF CONTENTS
|
1) Synthesis Options Summary
|
1) Synthesis Options Summary
|
2) HDL Compilation
|
2) HDL Compilation
|
3) Design Hierarchy Analysis
|
3) Design Hierarchy Analysis
|
4) HDL Analysis
|
4) HDL Analysis
|
5) HDL Synthesis
|
5) HDL Synthesis
|
5.1) HDL Synthesis Report
|
5.1) HDL Synthesis Report
|
6) Advanced HDL Synthesis
|
6) Advanced HDL Synthesis
|
6.1) Advanced HDL Synthesis Report
|
6.1) Advanced HDL Synthesis Report
|
7) Low Level Synthesis
|
7) Low Level Synthesis
|
8) Partition Report
|
8) Partition Report
|
9) Final Report
|
9) Final Report
|
9.1) Device utilization summary
|
9.1) Device utilization summary
|
9.2) Partition Resource Summary
|
9.2) Partition Resource Summary
|
9.3) TIMING REPORT
|
9.3) TIMING REPORT
|
|
|
|
|
=========================================================================
|
=========================================================================
|
* Synthesis Options Summary *
|
* Synthesis Options Summary *
|
=========================================================================
|
=========================================================================
|
---- Source Parameters
|
---- Source Parameters
|
Input File Name : "Display_Controller.prj"
|
Input File Name : "Display_Controller.prj"
|
Input Format : mixed
|
Input Format : mixed
|
Ignore Synthesis Constraint File : NO
|
Ignore Synthesis Constraint File : NO
|
|
|
---- Target Parameters
|
---- Target Parameters
|
Output File Name : "Display_Controller"
|
Output File Name : "Display_Controller"
|
Output Format : NGC
|
Output Format : NGC
|
Target Device : xc3s1000-4-ft256
|
Target Device : xc3s1000-4-ft256
|
|
|
---- Source Options
|
---- Source Options
|
Top Module Name : Display_Controller
|
Top Module Name : Display_Controller
|
Automatic FSM Extraction : YES
|
Automatic FSM Extraction : YES
|
FSM Encoding Algorithm : Auto
|
FSM Encoding Algorithm : Auto
|
Safe Implementation : No
|
Safe Implementation : No
|
FSM Style : lut
|
FSM Style : lut
|
RAM Extraction : Yes
|
RAM Extraction : Yes
|
RAM Style : Auto
|
RAM Style : Auto
|
ROM Extraction : Yes
|
ROM Extraction : Yes
|
Mux Style : Auto
|
Mux Style : Auto
|
Decoder Extraction : YES
|
Decoder Extraction : YES
|
Priority Encoder Extraction : YES
|
Priority Encoder Extraction : YES
|
Shift Register Extraction : YES
|
Shift Register Extraction : YES
|
Logical Shifter Extraction : YES
|
Logical Shifter Extraction : YES
|
XOR Collapsing : YES
|
XOR Collapsing : YES
|
ROM Style : Auto
|
ROM Style : Auto
|
Mux Extraction : YES
|
Mux Extraction : YES
|
Resource Sharing : YES
|
Resource Sharing : YES
|
Asynchronous To Synchronous : NO
|
Asynchronous To Synchronous : NO
|
Multiplier Style : auto
|
Multiplier Style : auto
|
Automatic Register Balancing : No
|
Automatic Register Balancing : No
|
|
|
---- Target Options
|
---- Target Options
|
Add IO Buffers : YES
|
Add IO Buffers : YES
|
Global Maximum Fanout : 500
|
Global Maximum Fanout : 500
|
Add Generic Clock Buffer(BUFG) : 8
|
Add Generic Clock Buffer(BUFG) : 8
|
Register Duplication : YES
|
Register Duplication : YES
|
Slice Packing : YES
|
Slice Packing : YES
|
Optimize Instantiated Primitives : NO
|
Optimize Instantiated Primitives : NO
|
Use Clock Enable : Yes
|
Use Clock Enable : Yes
|
Use Synchronous Set : Yes
|
Use Synchronous Set : Yes
|
Use Synchronous Reset : Yes
|
Use Synchronous Reset : Yes
|
Pack IO Registers into IOBs : auto
|
Pack IO Registers into IOBs : auto
|
Equivalent register Removal : YES
|
Equivalent register Removal : YES
|
|
|
---- General Options
|
---- General Options
|
Optimization Goal : Speed
|
Optimization Goal : Speed
|
Optimization Effort : 1
|
Optimization Effort : 1
|
Library Search Order : Display_Controller.lso
|
Library Search Order : Display_Controller.lso
|
Keep Hierarchy : NO
|
Keep Hierarchy : NO
|
Netlist Hierarchy : as_optimized
|
Netlist Hierarchy : as_optimized
|
RTL Output : Yes
|
RTL Output : Yes
|
Global Optimization : AllClockNets
|
Global Optimization : AllClockNets
|
Read Cores : YES
|
Read Cores : YES
|
Write Timing Constraints : NO
|
Write Timing Constraints : NO
|
Cross Clock Analysis : NO
|
Cross Clock Analysis : NO
|
Hierarchy Separator : /
|
Hierarchy Separator : /
|
Bus Delimiter : <>
|
Bus Delimiter : <>
|
Case Specifier : maintain
|
Case Specifier : maintain
|
Slice Utilization Ratio : 100
|
Slice Utilization Ratio : 100
|
BRAM Utilization Ratio : 100
|
BRAM Utilization Ratio : 100
|
Verilog 2001 : YES
|
Verilog 2001 : YES
|
Auto BRAM Packing : NO
|
Auto BRAM Packing : NO
|
Slice Utilization Ratio Delta : 5
|
Slice Utilization Ratio Delta : 5
|
|
|
=========================================================================
|
=========================================================================
|
|
|
|
|
=========================================================================
|
=========================================================================
|
* HDL Compilation *
|
* HDL Compilation *
|
=========================================================================
|
=========================================================================
|
Compiling verilog file "vga_display.v" in library work
|
Compiling verilog file "vga_display.v" in library work
|
Compiling verilog file "vga_controller.v" in library work
|
Compiling verilog file "vga_controller.v" in library work
|
Module compiled
|
Module compiled
|
Compiling verilog file "generate_add.v" in library work
|
Compiling verilog file "generate_add.v" in library work
|
Module compiled
|
Module compiled
|
Compiling verilog file "./fifo_generator_v4_3.v" in library work
|
Compiling verilog file "./fifo_generator_v4_3.v" in library work
|
Module compiled
|
Module compiled
|
Compiling verilog file "color_fsm.v" in library work
|
Compiling verilog file "color_fsm.v" in library work
|
Module compiled
|
Module compiled
|
Compiling verilog file "clock_divider.v" in library work
|
Compiling verilog file "clock_divider.v" in library work
|
Module compiled
|
Module compiled
|
Compiling verilog file "Display_Controller.v" in library work
|
Compiling verilog file "Display_Controller.v" in library work
|
Module compiled
|
Module compiled
|
Module compiled
|
Module compiled
|
No errors in compilation
|
No errors in compilation
|
Analysis of file <"Display_Controller.prj"> succeeded.
|
Analysis of file <"Display_Controller.prj"> succeeded.
|
|
|
|
|
=========================================================================
|
=========================================================================
|
* Design Hierarchy Analysis *
|
* Design Hierarchy Analysis *
|
=========================================================================
|
=========================================================================
|
Analyzing hierarchy for module in library .
|
Analyzing hierarchy for module in library .
|
|
|
Analyzing hierarchy for module in library with parameters.
|
Analyzing hierarchy for module in library with parameters.
|
NBIT = "00000000000000000000000000000010"
|
NBIT = "00000000000000000000000000000010"
|
NDIV = "00000000000000000000000000000010"
|
NDIV = "00000000000000000000000000000010"
|
|
|
Analyzing hierarchy for module in library with parameters.
|
Analyzing hierarchy for module in library with parameters.
|
NBIT = "00000000000000000000000000000100"
|
NBIT = "00000000000000000000000000000100"
|
NDIV = "00000000000000000000000000001010"
|
NDIV = "00000000000000000000000000001010"
|
|
|
Analyzing hierarchy for module in library with parameters.
|
Analyzing hierarchy for module in library with parameters.
|
NBIT = "00000000000000000000000000000101"
|
NBIT = "00000000000000000000000000000101"
|
NDIV = "00000000000000000000000000010100"
|
NDIV = "00000000000000000000000000010100"
|
|
|
Analyzing hierarchy for module in library with parameters.
|
Analyzing hierarchy for module in library with parameters.
|
HFP = "00000000000000000000001010001000"
|
HFP = "00000000000000000000001010001000"
|
HLINES = "00000000000000000000001010000000"
|
HLINES = "00000000000000000000001010000000"
|
HMAX = "00000000000000000000001100100000"
|
HMAX = "00000000000000000000001100100000"
|
HSP = "00000000000000000000001011101000"
|
HSP = "00000000000000000000001011101000"
|
SPP = "00000000000000000000000000000000"
|
SPP = "00000000000000000000000000000000"
|
VFP = "00000000000000000000000111100010"
|
VFP = "00000000000000000000000111100010"
|
VLINES = "00000000000000000000000111100000"
|
VLINES = "00000000000000000000000111100000"
|
VMAX = "00000000000000000000001000001101"
|
VMAX = "00000000000000000000001000001101"
|
VSP = "00000000000000000000000111100100"
|
VSP = "00000000000000000000000111100100"
|
|
|
Analyzing hierarchy for module in library with parameters.
|
Analyzing hierarchy for module in library with parameters.
|
pixel_1 = "000"
|
pixel_1 = "000"
|
pixel_2 = "001"
|
pixel_2 = "001"
|
pixel_3 = "010"
|
pixel_3 = "010"
|
pixel_4 = "011"
|
pixel_4 = "011"
|
pixel_5 = "100"
|
pixel_5 = "100"
|
xpos_end = "111000000"
|
xpos_end = "111000000"
|
xpos_start = "011000000"
|
xpos_start = "011000000"
|
ypos_end = "110110000"
|
ypos_end = "110110000"
|
ypos_start = "000110000"
|
ypos_start = "000110000"
|
|
|
Analyzing hierarchy for module in library with parameters.
|
Analyzing hierarchy for module in library with parameters.
|
score_pos = "111000010"
|
score_pos = "111000010"
|
xpos_end = "111000000"
|
xpos_end = "111000000"
|
xpos_start = "011000000"
|
xpos_start = "011000000"
|
ypos_end = "110110000"
|
ypos_end = "110110000"
|
ypos_start = "000110000"
|
ypos_start = "000110000"
|
|
|
Analyzing hierarchy for module in library .
|
Analyzing hierarchy for module in library .
|
|
|
|
|
=========================================================================
|
=========================================================================
|
* HDL Analysis *
|
* HDL Analysis *
|
=========================================================================
|
=========================================================================
|
Analyzing top module .
|
Analyzing top module .
|
WARNING:Xst:2211 - "./fifo_generator_v4_3.v" line 48: Instantiating black box module .
|
WARNING:Xst:2211 - "./fifo_generator_v4_3.v" line 48: Instantiating black box module .
|
Module is correct for synthesis.
|
Module is correct for synthesis.
|
|
|
Analyzing module in library .
|
Analyzing module in library .
|
NBIT = 32'sb00000000000000000000000000000010
|
NBIT = 32'sb00000000000000000000000000000010
|
NDIV = 32'sb00000000000000000000000000000010
|
NDIV = 32'sb00000000000000000000000000000010
|
Module is correct for synthesis.
|
Module is correct for synthesis.
|
|
|
Analyzing module in library .
|
Analyzing module in library .
|
NBIT = 32'sb00000000000000000000000000000100
|
NBIT = 32'sb00000000000000000000000000000100
|
NDIV = 32'sb00000000000000000000000000001010
|
NDIV = 32'sb00000000000000000000000000001010
|
Module is correct for synthesis.
|
Module is correct for synthesis.
|
|
|
Analyzing module in library .
|
Analyzing module in library .
|
NBIT = 32'sb00000000000000000000000000000101
|
NBIT = 32'sb00000000000000000000000000000101
|
NDIV = 32'sb00000000000000000000000000010100
|
NDIV = 32'sb00000000000000000000000000010100
|
Module is correct for synthesis.
|
Module is correct for synthesis.
|
|
|
Analyzing module in library .
|
Analyzing module in library .
|
HFP = 32'sb00000000000000000000001010001000
|
HFP = 32'sb00000000000000000000001010001000
|
HLINES = 32'sb00000000000000000000001010000000
|
HLINES = 32'sb00000000000000000000001010000000
|
HMAX = 32'sb00000000000000000000001100100000
|
HMAX = 32'sb00000000000000000000001100100000
|
HSP = 32'sb00000000000000000000001011101000
|
HSP = 32'sb00000000000000000000001011101000
|
SPP = 32'sb00000000000000000000000000000000
|
SPP = 32'sb00000000000000000000000000000000
|
VFP = 32'sb00000000000000000000000111100010
|
VFP = 32'sb00000000000000000000000111100010
|
VLINES = 32'sb00000000000000000000000111100000
|
VLINES = 32'sb00000000000000000000000111100000
|
VMAX = 32'sb00000000000000000000001000001101
|
VMAX = 32'sb00000000000000000000001000001101
|
VSP = 32'sb00000000000000000000000111100100
|
VSP = 32'sb00000000000000000000000111100100
|
Module is correct for synthesis.
|
Module is correct for synthesis.
|
|
|
Analyzing module in library .
|
Analyzing module in library .
|
pixel_1 = 3'b000
|
pixel_1 = 3'b000
|
pixel_2 = 3'b001
|
pixel_2 = 3'b001
|
pixel_3 = 3'b010
|
pixel_3 = 3'b010
|
pixel_4 = 3'b011
|
pixel_4 = 3'b011
|
pixel_5 = 3'b100
|
pixel_5 = 3'b100
|
xpos_end = 9'b111000000
|
xpos_end = 9'b111000000
|
xpos_start = 9'b011000000
|
xpos_start = 9'b011000000
|
ypos_end = 9'b110110000
|
ypos_end = 9'b110110000
|
ypos_start = 9'b000110000
|
ypos_start = 9'b000110000
|
WARNING:Xst:905 - "color_fsm.v" line 52: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
WARNING:Xst:905 - "color_fsm.v" line 52: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
, ,
|
, ,
|
Module is correct for synthesis.
|
Module is correct for synthesis.
|
|
|
Analyzing module in library .
|
Analyzing module in library .
|
score_pos = 9'b111000010
|
score_pos = 9'b111000010
|
xpos_end = 9'b111000000
|
xpos_end = 9'b111000000
|
xpos_start = 9'b011000000
|
xpos_start = 9'b011000000
|
ypos_end = 9'b110110000
|
ypos_end = 9'b110110000
|
ypos_start = 9'b000110000
|
ypos_start = 9'b000110000
|
Module is correct for synthesis.
|
Module is correct for synthesis.
|
|
|
Analyzing module in library .
|
Analyzing module in library .
|
Module is correct for synthesis.
|
Module is correct for synthesis.
|
|
|
|
|
=========================================================================
|
=========================================================================
|
* HDL Synthesis *
|
* HDL Synthesis *
|
=========================================================================
|
=========================================================================
|
|
|
Performing bidirectional port resolution...
|
Performing bidirectional port resolution...
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "clock_divider.v".
|
Related source file is "clock_divider.v".
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 2-bit up counter for signal .
|
Found 2-bit up counter for signal .
|
Found 2-bit comparator greatequal for signal created at line 38.
|
Found 2-bit comparator greatequal for signal created at line 38.
|
Found 2-bit comparator greater for signal created at line 40.
|
Found 2-bit comparator greater for signal created at line 40.
|
Summary:
|
Summary:
|
inferred 1 Counter(s).
|
inferred 1 Counter(s).
|
inferred 1 D-type flip-flop(s).
|
inferred 1 D-type flip-flop(s).
|
inferred 2 Comparator(s).
|
inferred 2 Comparator(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "clock_divider.v".
|
Related source file is "clock_divider.v".
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 4-bit up counter for signal .
|
Found 4-bit up counter for signal .
|
Found 4-bit comparator greatequal for signal created at line 38.
|
Found 4-bit comparator greatequal for signal created at line 38.
|
Found 4-bit comparator greater for signal created at line 40.
|
Found 4-bit comparator greater for signal created at line 40.
|
Summary:
|
Summary:
|
inferred 1 Counter(s).
|
inferred 1 Counter(s).
|
inferred 1 D-type flip-flop(s).
|
inferred 1 D-type flip-flop(s).
|
inferred 2 Comparator(s).
|
inferred 2 Comparator(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "clock_divider.v".
|
Related source file is "clock_divider.v".
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 5-bit up counter for signal .
|
Found 5-bit up counter for signal .
|
Found 5-bit comparator greatequal for signal created at line 38.
|
Found 5-bit comparator greatequal for signal created at line 38.
|
Found 5-bit comparator greater for signal created at line 40.
|
Found 5-bit comparator greater for signal created at line 40.
|
Summary:
|
Summary:
|
inferred 1 Counter(s).
|
inferred 1 Counter(s).
|
inferred 1 D-type flip-flop(s).
|
inferred 1 D-type flip-flop(s).
|
inferred 2 Comparator(s).
|
inferred 2 Comparator(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "vga_controller.v".
|
Related source file is "vga_controller.v".
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 11-bit up counter for signal .
|
Found 11-bit up counter for signal .
|
Found 11-bit up counter for signal .
|
Found 11-bit up counter for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 11-bit comparator greatequal for signal created at line 60.
|
Found 11-bit comparator greatequal for signal created at line 60.
|
Found 11-bit comparator less for signal created at line 60.
|
Found 11-bit comparator less for signal created at line 60.
|
Found 11-bit comparator less for signal created at line 67.
|
Found 11-bit comparator less for signal created at line 67.
|
Found 11-bit comparator less for signal created at line 67.
|
Found 11-bit comparator less for signal created at line 67.
|
Found 11-bit comparator greatequal for signal created at line 64.
|
Found 11-bit comparator greatequal for signal created at line 64.
|
Found 11-bit comparator less for signal created at line 64.
|
Found 11-bit comparator less for signal created at line 64.
|
Summary:
|
Summary:
|
inferred 2 Counter(s).
|
inferred 2 Counter(s).
|
inferred 3 D-type flip-flop(s).
|
inferred 3 D-type flip-flop(s).
|
inferred 6 Comparator(s).
|
inferred 6 Comparator(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "color_fsm.v".
|
Related source file is "color_fsm.v".
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
Found finite state machine for signal .
|
Found finite state machine for signal .
|
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
| States | 5 |
|
| States | 5 |
|
| Transitions | 9 |
|
| Transitions | 9 |
|
| Inputs | 1 |
|
| Inputs | 1 |
|
| Outputs | 5 |
|
| Outputs | 5 |
|
| Clock | clk_20MHz (rising_edge) |
|
| Clock | clk_20MHz (rising_edge) |
|
| Clock enable | pixel_state$not0000 (positive) |
|
| Clock enable | pixel_state$not0000 (positive) |
|
| Power Up State | 000 |
|
| Power Up State | 000 |
|
| Encoding | automatic |
|
| Encoding | automatic |
|
| Implementation | LUT |
|
| Implementation | LUT |
|
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 11-bit comparator greatequal for signal created at line 74.
|
Found 11-bit comparator greatequal for signal created at line 74.
|
Found 11-bit comparator greatequal for signal created at line 73.
|
Found 11-bit comparator greatequal for signal created at line 73.
|
Found 11-bit comparator less for signal created at line 74.
|
Found 11-bit comparator less for signal created at line 74.
|
Found 11-bit comparator less for signal created at line 73.
|
Found 11-bit comparator less for signal created at line 73.
|
Summary:
|
Summary:
|
inferred 1 Finite State Machine(s).
|
inferred 1 Finite State Machine(s).
|
inferred 5 D-type flip-flop(s).
|
inferred 5 D-type flip-flop(s).
|
inferred 4 Comparator(s).
|
inferred 4 Comparator(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "vga_display.v".
|
Related source file is "vga_display.v".
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 1-bit register for signal .
|
Found 11-bit comparator greatequal for signal created at line 52.
|
Found 11-bit comparator greatequal for signal created at line 52.
|
Found 11-bit comparator greatequal for signal created at line 53.
|
Found 11-bit comparator greatequal for signal created at line 53.
|
Found 11-bit comparator less for signal created at line 52.
|
Found 11-bit comparator less for signal created at line 52.
|
Found 11-bit comparator less for signal created at line 53.
|
Found 11-bit comparator less for signal created at line 53.
|
Summary:
|
Summary:
|
inferred 3 D-type flip-flop(s).
|
inferred 3 D-type flip-flop(s).
|
inferred 4 Comparator(s).
|
inferred 4 Comparator(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "generate_add.v".
|
Related source file is "generate_add.v".
|
Found 16-bit up counter for signal .
|
Found 16-bit up counter for signal .
|
Summary:
|
Summary:
|
inferred 1 Counter(s).
|
inferred 1 Counter(s).
|
Unit synthesized.
|
Unit synthesized.
|
|
|
|
|
Synthesizing Unit .
|
Synthesizing Unit .
|
Related source file is "Display_Controller.v".
|
Related source file is "Display_Controller.v".
|
Unit synthesized.
|
Unit synthesized.
|
|
|
|
|
=========================================================================
|
=========================================================================
|
HDL Synthesis Report
|
HDL Synthesis Report
|
|
|
Macro Statistics
|
Macro Statistics
|
# Counters : 6
|
# Counters : 6
|
11-bit up counter : 2
|
11-bit up counter : 2
|
16-bit up counter : 1
|
16-bit up counter : 1
|
2-bit up counter : 1
|
2-bit up counter : 1
|
4-bit up counter : 1
|
4-bit up counter : 1
|
5-bit up counter : 1
|
5-bit up counter : 1
|
# Registers : 14
|
# Registers : 14
|
1-bit register : 14
|
1-bit register : 14
|
# Latches : 1
|
# Latches : 1
|
1-bit latch : 1
|
1-bit latch : 1
|
# Comparators : 20
|
# Comparators : 20
|
11-bit comparator greatequal : 6
|
11-bit comparator greatequal : 6
|
11-bit comparator less : 8
|
11-bit comparator less : 8
|
2-bit comparator greatequal : 1
|
2-bit comparator greatequal : 1
|
2-bit comparator greater : 1
|
2-bit comparator greater : 1
|
4-bit comparator greatequal : 1
|
4-bit comparator greatequal : 1
|
4-bit comparator greater : 1
|
4-bit comparator greater : 1
|
5-bit comparator greatequal : 1
|
5-bit comparator greatequal : 1
|
5-bit comparator greater : 1
|
5-bit comparator greater : 1
|
|
|
=========================================================================
|
=========================================================================
|
|
|
=========================================================================
|
=========================================================================
|
* Advanced HDL Synthesis *
|
* Advanced HDL Synthesis *
|
=========================================================================
|
=========================================================================
|
|
|
Analyzing FSM for best encoding.
|
Analyzing FSM for best encoding.
|
Optimizing FSM on signal with gray encoding.
|
Optimizing FSM on signal with gray encoding.
|
-------------------
|
-------------------
|
State | Encoding
|
State | Encoding
|
-------------------
|
-------------------
|
000 | 000
|
000 | 000
|
001 | 001
|
001 | 001
|
010 | 011
|
010 | 011
|
011 | 010
|
011 | 010
|
100 | 110
|
100 | 110
|
-------------------
|
-------------------
|
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx\10.1\ISE.
|
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx\10.1\ISE.
|
Reading core .
|
Reading core .
|
Loading core for timing and area information for instance .
|
Loading core for timing and area information for instance .
|
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block count.
|
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block count.
|
You should achieve better results by setting this init to 1.
|
You should achieve better results by setting this init to 1.
|
|
|
=========================================================================
|
=========================================================================
|
Advanced HDL Synthesis Report
|
Advanced HDL Synthesis Report
|
|
|
Macro Statistics
|
Macro Statistics
|
# Counters : 6
|
# Counters : 6
|
11-bit up counter : 2
|
11-bit up counter : 2
|
16-bit up counter : 1
|
16-bit up counter : 1
|
2-bit up counter : 1
|
2-bit up counter : 1
|
4-bit up counter : 1
|
4-bit up counter : 1
|
5-bit up counter : 1
|
5-bit up counter : 1
|
# Registers : 17
|
# Registers : 17
|
Flip-Flops : 17
|
Flip-Flops : 17
|
# Latches : 1
|
# Latches : 1
|
1-bit latch : 1
|
1-bit latch : 1
|
# Comparators : 20
|
# Comparators : 20
|
11-bit comparator greatequal : 6
|
11-bit comparator greatequal : 6
|
11-bit comparator less : 8
|
11-bit comparator less : 8
|
2-bit comparator greatequal : 1
|
2-bit comparator greatequal : 1
|
2-bit comparator greater : 1
|
2-bit comparator greater : 1
|
4-bit comparator greatequal : 1
|
4-bit comparator greatequal : 1
|
4-bit comparator greater : 1
|
4-bit comparator greater : 1
|
5-bit comparator greatequal : 1
|
5-bit comparator greatequal : 1
|
5-bit comparator greater : 1
|
5-bit comparator greater : 1
|
|
|
=========================================================================
|
=========================================================================
|
|
|
=========================================================================
|
=========================================================================
|
* Low Level Synthesis *
|
* Low Level Synthesis *
|
=========================================================================
|
=========================================================================
|
WARNING:Xst:1426 - The value init of the FF/Latch count hinder the constant cleaning in the block color_fsm.
|
WARNING:Xst:1426 - The value init of the FF/Latch count hinder the constant cleaning in the block color_fsm.
|
You should achieve better results by setting this init to 1.
|
You should achieve better results by setting this init to 1.
|
|
|
Optimizing unit ...
|
Optimizing unit ...
|
|
|
Optimizing unit ...
|
Optimizing unit ...
|
|
|
Mapping all equations...
|
Mapping all equations...
|
Building and optimizing final netlist ...
|
Building and optimizing final netlist ...
|
Found area constraint ratio of 100 (+ 5) on block Display_Controller, actual ratio is 2.
|
Found area constraint ratio of 100 (+ 5) on block Display_Controller, actual ratio is 2.
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch :
|
|
|
Final Macro Processing ...
|
Final Macro Processing ...
|
|
|
=========================================================================
|
=========================================================================
|
Final Register Report
|
Final Register Report
|
|
|
Macro Statistics
|
Macro Statistics
|
# Registers : 66
|
# Registers : 66
|
Flip-Flops : 66
|
Flip-Flops : 66
|
|
|
=========================================================================
|
=========================================================================
|
|
|
=========================================================================
|
=========================================================================
|
* Partition Report *
|
* Partition Report *
|
=========================================================================
|
=========================================================================
|
|
|
Partition Implementation Status
|
Partition Implementation Status
|
-------------------------------
|
-------------------------------
|
|
|
No Partitions were found in this design.
|
No Partitions were found in this design.
|
|
|
-------------------------------
|
-------------------------------
|
|
|
=========================================================================
|
=========================================================================
|
* Final Report *
|
* Final Report *
|
=========================================================================
|
=========================================================================
|
Final Results
|
Final Results
|
RTL Top Level Output File Name : Display_Controller.ngr
|
RTL Top Level Output File Name : Display_Controller.ngr
|
Top Level Output File Name : Display_Controller
|
Top Level Output File Name : Display_Controller
|
Output Format : NGC
|
Output Format : NGC
|
Optimization Goal : Speed
|
Optimization Goal : Speed
|
Keep Hierarchy : NO
|
Keep Hierarchy : NO
|
|
|
Design Statistics
|
Design Statistics
|
# IOs : 44
|
# IOs : 44
|
|
|
Cell Usage :
|
Cell Usage :
|
# BELS : 510
|
# BELS : 510
|
# GND : 2
|
# GND : 2
|
# INV : 9
|
# INV : 9
|
# LUT1 : 63
|
# LUT1 : 63
|
# LUT2 : 52
|
# LUT2 : 52
|
# LUT2_L : 8
|
# LUT2_L : 8
|
# LUT3 : 60
|
# LUT3 : 60
|
# LUT3_D : 2
|
# LUT3_D : 2
|
# LUT3_L : 3
|
# LUT3_L : 3
|
# LUT4 : 108
|
# LUT4 : 108
|
# LUT4_D : 5
|
# LUT4_D : 5
|
# LUT4_L : 11
|
# LUT4_L : 11
|
# MUXCY : 95
|
# MUXCY : 95
|
# MUXF5 : 18
|
# MUXF5 : 18
|
# MUXF6 : 9
|
# MUXF6 : 9
|
# VCC : 2
|
# VCC : 2
|
# XORCY : 63
|
# XORCY : 63
|
# FlipFlops/Latches : 267
|
# FlipFlops/Latches : 267
|
# FD : 4
|
# FD : 4
|
# FDC : 112
|
# FDC : 112
|
# FDCE : 67
|
# FDCE : 67
|
# FDE : 14
|
# FDE : 14
|
# FDP : 9
|
# FDP : 9
|
# FDPE : 5
|
# FDPE : 5
|
# FDR : 44
|
# FDR : 44
|
# FDRE : 11
|
# FDRE : 11
|
# LDE : 1
|
# LDE : 1
|
# RAMS : 15
|
# RAMS : 15
|
# RAMB16_S1_S1 : 7
|
# RAMB16_S1_S1 : 7
|
# RAMB16_S9_S9 : 8
|
# RAMB16_S9_S9 : 8
|
# Clock Buffers : 3
|
# Clock Buffers : 3
|
# BUFG : 2
|
# BUFG : 2
|
# BUFGP : 1
|
# BUFGP : 1
|
# IO Buffers : 43
|
# IO Buffers : 43
|
# IBUF : 1
|
# IBUF : 1
|
# OBUF : 42
|
# OBUF : 42
|
=========================================================================
|
=========================================================================
|
|
|
Device utilization summary:
|
Device utilization summary:
|
---------------------------
|
---------------------------
|
|
|
Selected Device : 3s1000ft256-4
|
Selected Device : 3s1000ft256-4
|
|
|
Number of Slices: 221 out of 7680 2%
|
Number of Slices: 221 out of 7680 2%
|
Number of Slice Flip Flops: 267 out of 15360 1%
|
Number of Slice Flip Flops: 267 out of 15360 1%
|
Number of 4 input LUTs: 321 out of 15360 2%
|
Number of 4 input LUTs: 321 out of 15360 2%
|
Number of IOs: 44
|
Number of IOs: 44
|
Number of bonded IOBs: 44 out of 173 25%
|
Number of bonded IOBs: 44 out of 173 25%
|
Number of BRAMs: 15 out of 24 62%
|
Number of BRAMs: 15 out of 24 62%
|
Number of GCLKs: 3 out of 8 37%
|
Number of GCLKs: 3 out of 8 37%
|
|
|
---------------------------
|
---------------------------
|
Partition Resource Summary:
|
Partition Resource Summary:
|
---------------------------
|
---------------------------
|
|
|
No Partitions were found in this design.
|
No Partitions were found in this design.
|
|
|
---------------------------
|
---------------------------
|
|
|
|
|
=========================================================================
|
=========================================================================
|
TIMING REPORT
|
TIMING REPORT
|
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
GENERATED AFTER PLACE-and-ROUTE.
|
GENERATED AFTER PLACE-and-ROUTE.
|
|
|
Clock Information:
|
Clock Information:
|
------------------
|
------------------
|
-------------------------------------------------+------------------------+-------+
|
-------------------------------------------------+------------------------+-------+
|
Clock Signal | Clock buffer(FF name) | Load |
|
Clock Signal | Clock buffer(FF name) | Load |
|
-------------------------------------------------+------------------------+-------+
|
-------------------------------------------------+------------------------+-------+
|
clk2/div_clk1 | BUFG | 103 |
|
clk2/div_clk1 | BUFG | 103 |
|
clk1/div_clk1 | BUFG | 160 |
|
clk1/div_clk1 | BUFG | 160 |
|
clk | BUFGP | 3 |
|
clk | BUFGP | 3 |
|
clk3/div_clk | NONE(add1/addr_0) | 16 |
|
clk3/div_clk | NONE(add1/addr_0) | 16 |
|
vga2/count_and0000(vga2/count_and0000_wg_cy<5>:O)| NONE(*)(vga2/count) | 1 |
|
vga2/count_and0000(vga2/count_and0000_wg_cy<5>:O)| NONE(*)(vga2/count) | 1 |
|
-------------------------------------------------+------------------------+-------+
|
-------------------------------------------------+------------------------+-------+
|
(*) This 1 clock signal(s) are generated by combinatorial logic,
|
(*) This 1 clock signal(s) are generated by combinatorial logic,
|
and XST is not able to identify which are the primary clock signals.
|
and XST is not able to identify which are the primary clock signals.
|
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
|
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
|
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
|
|
Asynchronous Control Signals Information:
|
Asynchronous Control Signals Information:
|
----------------------------------------
|
----------------------------------------
|
-----------------------------------------------------------------------------------+------------------------------------------------------+-------+
|
-----------------------------------------------------------------------------------+------------------------------------------------------+-------+
|
Control Signal | Buffer(FF name) | Load |
|
Control Signal | Buffer(FF name) | Load |
|
-----------------------------------------------------------------------------------+------------------------------------------------------+-------+
|
-----------------------------------------------------------------------------------+------------------------------------------------------+-------+
|
fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg<1>(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_1:Q)| NONE(fifo1/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_9)| 56 |
|
fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg<1>(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_1:Q)| NONE(fifo1/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_9)| 56 |
|
fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg<0>(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg_0:Q)| NONE(fifo1/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4)| 56 |
|
fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg<0>(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg_0:Q)| NONE(fifo1/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4)| 56 |
|
fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i)| 44 |
|
fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i)| 44 |
|
fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(fifo1/BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0) | 30 |
|
fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(fifo1/BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0) | 30 |
|
fifo1/BU2/U0/grf.rf/rstblk/rd_rst_comb(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O) | NONE(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_2) | 3 |
|
fifo1/BU2/U0/grf.rf/rstblk/rd_rst_comb(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O) | NONE(fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_2) | 3 |
|
fifo1/BU2/U0/grf.rf/rstblk/wr_rst_comb(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O) | NONE(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg_1) | 2 |
|
fifo1/BU2/U0/grf.rf/rstblk/wr_rst_comb(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O) | NONE(fifo1/BU2/U0/grf.rf/rstblk/wr_rst_reg_1) | 2 |
|
reset | IBUF | 2 |
|
reset | IBUF | 2 |
|
-----------------------------------------------------------------------------------+------------------------------------------------------+-------+
|
-----------------------------------------------------------------------------------+------------------------------------------------------+-------+
|
|
|
Timing Summary:
|
Timing Summary:
|
---------------
|
---------------
|
Speed Grade: -4
|
Speed Grade: -4
|
|
|
Minimum period: 7.055ns (Maximum Frequency: 141.743MHz)
|
Minimum period: 7.055ns (Maximum Frequency: 141.743MHz)
|
Minimum input arrival time before clock: 5.937ns
|
Minimum input arrival time before clock: 5.937ns
|
Maximum output required time after clock: 8.839ns
|
Maximum output required time after clock: 8.839ns
|
Maximum combinational path delay: No path found
|
Maximum combinational path delay: No path found
|
|
|
Timing Detail:
|
Timing Detail:
|
--------------
|
--------------
|
All values displayed in nanoseconds (ns)
|
All values displayed in nanoseconds (ns)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default period analysis for Clock 'clk2/div_clk1'
|
Timing constraint: Default period analysis for Clock 'clk2/div_clk1'
|
Clock period: 5.855ns (frequency: 170.794MHz)
|
Clock period: 5.855ns (frequency: 170.794MHz)
|
Total number of paths / destination ports: 555 / 213
|
Total number of paths / destination ports: 555 / 213
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Delay: 5.855ns (Levels of Logic = 2)
|
Delay: 5.855ns (Levels of Logic = 2)
|
Source: fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_0 (FF)
|
Source: fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_0 (FF)
|
Destination: fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r/v2_noinit.ram/dp9x9.ram (RAM)
|
Destination: fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r/v2_noinit.ram/dp9x9.ram (RAM)
|
Source Clock: clk2/div_clk1 rising
|
Source Clock: clk2/div_clk1 rising
|
Destination Clock: clk2/div_clk1 rising
|
Destination Clock: clk2/div_clk1 rising
|
|
|
Data Path: fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_0 to fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r/v2_noinit.ram/dp9x9.ram
|
Data Path: fifo1/BU2/U0/grf.rf/rstblk/rd_rst_reg_0 to fifo1/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r/v2_noinit.ram/dp9x9.ram
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDP:C->Q 16 0.720 1.305 U0/grf.rf/rstblk/rd_rst_reg_0 (U0/grf.rf/rstblk/rd_rst_reg<0>)
|
FDP:C->Q 16 0.720 1.305 U0/grf.rf/rstblk/rd_rst_reg_0 (U0/grf.rf/rstblk/rd_rst_reg<0>)
|
LUT3:I2->O 18 0.551 1.443 U0/grf.rf/mem/tmp_ram_rd_en1 (U0/grf.rf/mem/tmp_ram_rd_en)
|
LUT3:I2->O 18 0.551 1.443 U0/grf.rf/mem/tmp_ram_rd_en1 (U0/grf.rf/mem/tmp_ram_rd_en)
|
LUT4:I3->O 1 0.551 0.801 U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/bindec_b.bindec_inst_b/enout_7_mux00001 (U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/enb_array<7>)
|
LUT4:I3->O 1 0.551 0.801 U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/bindec_b.bindec_inst_b/enout_7_mux00001 (U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/enb_array<7>)
|
RAMB16_S9_S9:ENB 0.484 U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r/v2_noinit.ram/dp9x9.ram
|
RAMB16_S9_S9:ENB 0.484 U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[14].ram.r/v2_noinit.ram/dp9x9.ram
|
----------------------------------------
|
----------------------------------------
|
Total 5.855ns (2.306ns logic, 3.549ns route)
|
Total 5.855ns (2.306ns logic, 3.549ns route)
|
(39.4% logic, 60.6% route)
|
(39.4% logic, 60.6% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default period analysis for Clock 'clk1/div_clk1'
|
Timing constraint: Default period analysis for Clock 'clk1/div_clk1'
|
Clock period: 7.055ns (frequency: 141.743MHz)
|
Clock period: 7.055ns (frequency: 141.743MHz)
|
Total number of paths / destination ports: 1524 / 329
|
Total number of paths / destination ports: 1524 / 329
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Delay: 7.055ns (Levels of Logic = 3)
|
Delay: 7.055ns (Levels of Logic = 3)
|
Source: vga1/vcounter_0 (FF)
|
Source: vga1/vcounter_0 (FF)
|
Destination: vga1/vcounter_0 (FF)
|
Destination: vga1/vcounter_0 (FF)
|
Source Clock: clk1/div_clk1 rising
|
Source Clock: clk1/div_clk1 rising
|
Destination Clock: clk1/div_clk1 rising
|
Destination Clock: clk1/div_clk1 rising
|
|
|
Data Path: vga1/vcounter_0 to vga1/vcounter_0
|
Data Path: vga1/vcounter_0 to vga1/vcounter_0
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDRE:C->Q 3 0.720 1.246 vga1/vcounter_0 (vga1/vcounter_0)
|
FDRE:C->Q 3 0.720 1.246 vga1/vcounter_0 (vga1/vcounter_0)
|
LUT4:I0->O 1 0.551 1.140 vga1/vcounter_or000010 (vga1/vcounter_or000010)
|
LUT4:I0->O 1 0.551 1.140 vga1/vcounter_or000010 (vga1/vcounter_or000010)
|
LUT4_L:I0->LO 1 0.551 0.126 vga1/vcounter_or000075_SW0 (N27)
|
LUT4_L:I0->LO 1 0.551 0.126 vga1/vcounter_or000075_SW0 (N27)
|
LUT4:I3->O 11 0.551 1.144 vga1/vcounter_or000075 (vga1/vcounter_or0000)
|
LUT4:I3->O 11 0.551 1.144 vga1/vcounter_or000075 (vga1/vcounter_or0000)
|
FDRE:R 1.026 vga1/vcounter_0
|
FDRE:R 1.026 vga1/vcounter_0
|
----------------------------------------
|
----------------------------------------
|
Total 7.055ns (3.399ns logic, 3.656ns route)
|
Total 7.055ns (3.399ns logic, 3.656ns route)
|
(48.2% logic, 51.8% route)
|
(48.2% logic, 51.8% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default period analysis for Clock 'clk'
|
Timing constraint: Default period analysis for Clock 'clk'
|
Clock period: 4.430ns (frequency: 225.734MHz)
|
Clock period: 4.430ns (frequency: 225.734MHz)
|
Total number of paths / destination ports: 9 / 5
|
Total number of paths / destination ports: 9 / 5
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Delay: 4.430ns (Levels of Logic = 1)
|
Delay: 4.430ns (Levels of Logic = 1)
|
Source: clk1/count_0 (FF)
|
Source: clk1/count_0 (FF)
|
Destination: clk1/count_0 (FF)
|
Destination: clk1/count_0 (FF)
|
Source Clock: clk rising
|
Source Clock: clk rising
|
Destination Clock: clk rising
|
Destination Clock: clk rising
|
|
|
Data Path: clk1/count_0 to clk1/count_0
|
Data Path: clk1/count_0 to clk1/count_0
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDR:C->Q 4 0.720 1.256 clk1/count_0 (clk1/count_0)
|
FDR:C->Q 4 0.720 1.256 clk1/count_0 (clk1/count_0)
|
LUT2:I0->O 2 0.551 0.877 clk1/count_cmp_ge00001 (clk1/count_cmp_ge0000)
|
LUT2:I0->O 2 0.551 0.877 clk1/count_cmp_ge00001 (clk1/count_cmp_ge0000)
|
FDR:R 1.026 clk1/count_0
|
FDR:R 1.026 clk1/count_0
|
----------------------------------------
|
----------------------------------------
|
Total 4.430ns (2.297ns logic, 2.133ns route)
|
Total 4.430ns (2.297ns logic, 2.133ns route)
|
(51.9% logic, 48.1% route)
|
(51.9% logic, 48.1% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default period analysis for Clock 'clk3/div_clk'
|
Timing constraint: Default period analysis for Clock 'clk3/div_clk'
|
Clock period: 6.327ns (frequency: 158.053MHz)
|
Clock period: 6.327ns (frequency: 158.053MHz)
|
Total number of paths / destination ports: 392 / 32
|
Total number of paths / destination ports: 392 / 32
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Delay: 6.327ns (Levels of Logic = 2)
|
Delay: 6.327ns (Levels of Logic = 2)
|
Source: add1/addr_6 (FF)
|
Source: add1/addr_6 (FF)
|
Destination: add1/addr_0 (FF)
|
Destination: add1/addr_0 (FF)
|
Source Clock: clk3/div_clk rising
|
Source Clock: clk3/div_clk rising
|
Destination Clock: clk3/div_clk rising
|
Destination Clock: clk3/div_clk rising
|
|
|
Data Path: add1/addr_6 to add1/addr_0
|
Data Path: add1/addr_6 to add1/addr_0
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDR:C->Q 3 0.720 1.246 add1/addr_6 (add1/addr_6)
|
FDR:C->Q 3 0.720 1.246 add1/addr_6 (add1/addr_6)
|
LUT4:I0->O 1 0.551 0.996 add1/addr_and000016 (add1/addr_and000016)
|
LUT4:I0->O 1 0.551 0.996 add1/addr_and000016 (add1/addr_and000016)
|
LUT4:I1->O 16 0.551 1.237 add1/addr_and000059 (add1/addr_and0000)
|
LUT4:I1->O 16 0.551 1.237 add1/addr_and000059 (add1/addr_and0000)
|
FDR:R 1.026 add1/addr_0
|
FDR:R 1.026 add1/addr_0
|
----------------------------------------
|
----------------------------------------
|
Total 6.327ns (2.848ns logic, 3.479ns route)
|
Total 6.327ns (2.848ns logic, 3.479ns route)
|
(45.0% logic, 55.0% route)
|
(45.0% logic, 55.0% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default period analysis for Clock 'vga2/count_and0000'
|
Timing constraint: Default period analysis for Clock 'vga2/count_and0000'
|
Clock period: 3.797ns (frequency: 263.366MHz)
|
Clock period: 3.797ns (frequency: 263.366MHz)
|
Total number of paths / destination ports: 1 / 1
|
Total number of paths / destination ports: 1 / 1
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Delay: 3.797ns (Levels of Logic = 1)
|
Delay: 3.797ns (Levels of Logic = 1)
|
Source: vga2/count (LATCH)
|
Source: vga2/count (LATCH)
|
Destination: vga2/count (LATCH)
|
Destination: vga2/count (LATCH)
|
Source Clock: vga2/count_and0000 falling
|
Source Clock: vga2/count_and0000 falling
|
Destination Clock: vga2/count_and0000 falling
|
Destination Clock: vga2/count_and0000 falling
|
|
|
Data Path: vga2/count to vga2/count
|
Data Path: vga2/count to vga2/count
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
LDE:G->Q 10 0.633 1.134 vga2/count (vga2/count)
|
LDE:G->Q 10 0.633 1.134 vga2/count (vga2/count)
|
INV:I->O 2 0.551 0.877 vga2/read_memory1_INV_0 (read_memory_OBUF)
|
INV:I->O 2 0.551 0.877 vga2/read_memory1_INV_0 (read_memory_OBUF)
|
LDE:GE 0.602 vga2/count
|
LDE:GE 0.602 vga2/count
|
----------------------------------------
|
----------------------------------------
|
Total 3.797ns (1.786ns logic, 2.011ns route)
|
Total 3.797ns (1.786ns logic, 2.011ns route)
|
(47.0% logic, 53.0% route)
|
(47.0% logic, 53.0% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1/div_clk1'
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1/div_clk1'
|
Total number of paths / destination ports: 37 / 34
|
Total number of paths / destination ports: 37 / 34
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 5.937ns (Levels of Logic = 3)
|
Offset: 5.937ns (Levels of Logic = 3)
|
Source: reset (PAD)
|
Source: reset (PAD)
|
Destination: vga2/pixel_state_FFd3 (FF)
|
Destination: vga2/pixel_state_FFd3 (FF)
|
Destination Clock: clk1/div_clk1 rising
|
Destination Clock: clk1/div_clk1 rising
|
|
|
Data Path: reset to vga2/pixel_state_FFd3
|
Data Path: reset to vga2/pixel_state_FFd3
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
IBUF:I->O 13 0.821 1.365 reset_IBUF (reset_IBUF)
|
IBUF:I->O 13 0.821 1.365 reset_IBUF (reset_IBUF)
|
LUT2:I1->O 1 0.551 1.140 vga2/red_in_not0001296_SW1 (N24)
|
LUT2:I1->O 1 0.551 1.140 vga2/red_in_not0001296_SW1 (N24)
|
LUT4:I0->O 3 0.551 0.907 vga2/pixel_state_not00011 (vga2/pixel_state_not0001)
|
LUT4:I0->O 3 0.551 0.907 vga2/pixel_state_not00011 (vga2/pixel_state_not0001)
|
FDE:CE 0.602 vga2/pixel_state_FFd3
|
FDE:CE 0.602 vga2/pixel_state_FFd3
|
----------------------------------------
|
----------------------------------------
|
Total 5.937ns (2.525ns logic, 3.412ns route)
|
Total 5.937ns (2.525ns logic, 3.412ns route)
|
(42.5% logic, 57.5% route)
|
(42.5% logic, 57.5% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'vga2/count_and0000'
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'vga2/count_and0000'
|
Total number of paths / destination ports: 2 / 2
|
Total number of paths / destination ports: 2 / 2
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 8.839ns (Levels of Logic = 2)
|
Offset: 8.839ns (Levels of Logic = 2)
|
Source: vga2/count (LATCH)
|
Source: vga2/count (LATCH)
|
Destination: read_memory (PAD)
|
Destination: read_memory (PAD)
|
Source Clock: vga2/count_and0000 falling
|
Source Clock: vga2/count_and0000 falling
|
|
|
Data Path: vga2/count to read_memory
|
Data Path: vga2/count to read_memory
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
LDE:G->Q 10 0.633 1.134 vga2/count (vga2/count)
|
LDE:G->Q 10 0.633 1.134 vga2/count (vga2/count)
|
INV:I->O 2 0.551 0.877 vga2/read_memory1_INV_0 (read_memory_OBUF)
|
INV:I->O 2 0.551 0.877 vga2/read_memory1_INV_0 (read_memory_OBUF)
|
OBUF:I->O 5.644 read_memory_OBUF (read_memory)
|
OBUF:I->O 5.644 read_memory_OBUF (read_memory)
|
----------------------------------------
|
----------------------------------------
|
Total 8.839ns (6.828ns logic, 2.011ns route)
|
Total 8.839ns (6.828ns logic, 2.011ns route)
|
(77.2% logic, 22.8% route)
|
(77.2% logic, 22.8% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk1/div_clk1'
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk1/div_clk1'
|
Total number of paths / destination ports: 6 / 6
|
Total number of paths / destination ports: 6 / 6
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 7.241ns (Levels of Logic = 2)
|
Offset: 7.241ns (Levels of Logic = 2)
|
Source: fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (FF)
|
Source: fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (FF)
|
Destination: fifo_full (PAD)
|
Destination: fifo_full (PAD)
|
Source Clock: clk1/div_clk1 rising
|
Source Clock: clk1/div_clk1 rising
|
|
|
Data Path: fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i to fifo_full
|
Data Path: fifo1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i to fifo_full
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDP:C->Q 2 0.720 0.877 U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (full)
|
FDP:C->Q 2 0.720 0.877 U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (full)
|
end scope: 'BU2'
|
end scope: 'BU2'
|
end scope: 'fifo1'
|
end scope: 'fifo1'
|
OBUF:I->O 5.644 fifo_full_OBUF (fifo_full)
|
OBUF:I->O 5.644 fifo_full_OBUF (fifo_full)
|
----------------------------------------
|
----------------------------------------
|
Total 7.241ns (6.364ns logic, 0.877ns route)
|
Total 7.241ns (6.364ns logic, 0.877ns route)
|
(87.9% logic, 12.1% route)
|
(87.9% logic, 12.1% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk2/div_clk1'
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk2/div_clk1'
|
Total number of paths / destination ports: 1 / 1
|
Total number of paths / destination ports: 1 / 1
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 7.241ns (Levels of Logic = 2)
|
Offset: 7.241ns (Levels of Logic = 2)
|
Source: fifo1/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i (FF)
|
Source: fifo1/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i (FF)
|
Destination: fifo_empty (PAD)
|
Destination: fifo_empty (PAD)
|
Source Clock: clk2/div_clk1 rising
|
Source Clock: clk2/div_clk1 rising
|
|
|
Data Path: fifo1/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i to fifo_empty
|
Data Path: fifo1/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i to fifo_empty
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDP:C->Q 2 0.720 0.877 U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i (empty)
|
FDP:C->Q 2 0.720 0.877 U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i (empty)
|
end scope: 'BU2'
|
end scope: 'BU2'
|
end scope: 'fifo1'
|
end scope: 'fifo1'
|
OBUF:I->O 5.644 fifo_empty_OBUF (fifo_empty)
|
OBUF:I->O 5.644 fifo_empty_OBUF (fifo_empty)
|
----------------------------------------
|
----------------------------------------
|
Total 7.241ns (6.364ns logic, 0.877ns route)
|
Total 7.241ns (6.364ns logic, 0.877ns route)
|
(87.9% logic, 12.1% route)
|
(87.9% logic, 12.1% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk3/div_clk'
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk3/div_clk'
|
Total number of paths / destination ports: 16 / 16
|
Total number of paths / destination ports: 16 / 16
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 7.271ns (Levels of Logic = 1)
|
Offset: 7.271ns (Levels of Logic = 1)
|
Source: add1/addr_15 (FF)
|
Source: add1/addr_15 (FF)
|
Destination: addr<15> (PAD)
|
Destination: addr<15> (PAD)
|
Source Clock: clk3/div_clk rising
|
Source Clock: clk3/div_clk rising
|
|
|
Data Path: add1/addr_15 to addr<15>
|
Data Path: add1/addr_15 to addr<15>
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDR:C->Q 3 0.720 0.907 add1/addr_15 (add1/addr_15)
|
FDR:C->Q 3 0.720 0.907 add1/addr_15 (add1/addr_15)
|
OBUF:I->O 5.644 addr_15_OBUF (addr<15>)
|
OBUF:I->O 5.644 addr_15_OBUF (addr<15>)
|
----------------------------------------
|
----------------------------------------
|
Total 7.271ns (6.364ns logic, 0.907ns route)
|
Total 7.271ns (6.364ns logic, 0.907ns route)
|
(87.5% logic, 12.5% route)
|
(87.5% logic, 12.5% route)
|
|
|
=========================================================================
|
=========================================================================
|
|
|
|
|
Total REAL time to Xst completion: 16.00 secs
|
Total REAL time to Xst completion: 16.00 secs
|
Total CPU time to Xst completion: 15.63 secs
|
Total CPU time to Xst completion: 15.63 secs
|
|
|
-->
|
-->
|
|
|
Total memory usage is 159604 kilobytes
|
Total memory usage is 159604 kilobytes
|
|
|
Number of errors : 0 ( 0 filtered)
|
Number of errors : 0 ( 0 filtered)
|
Number of warnings : 8 ( 0 filtered)
|
Number of warnings : 8 ( 0 filtered)
|
Number of infos : 9 ( 0 filtered)
|
Number of infos : 9 ( 0 filtered)
|
|
|
|
|
