`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 00:56:57 11/20/2008
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// Create Date: 00:56:57 11/20/2008
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// Design Name:
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// Design Name:
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// Module Name: Display_Controller
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// Module Name: Display_Controller
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module Display_Controller(reset,clk,red_out,green_out,blue_out,v_sync,h_sync,fifo_full,fifo_empty,addr,pixel_color,write_memory,read_memory,chip_enable);
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module Display_Controller(reset,clk,red_out,green_out,blue_out,v_sync,h_sync,fifo_full,fifo_empty,addr,pixel_color,write_memory,read_memory,chip_enable);
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//Inputs
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//Inputs
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input clk,reset;
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input clk,reset;
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//Outputs
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//Outputs
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output red_out, green_out, blue_out;
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output red_out, green_out, blue_out;
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output v_sync, h_sync;
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output v_sync, h_sync;
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output fifo_full,fifo_empty,read_memory,write_memory,chip_enable;
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output fifo_full,fifo_empty,read_memory,write_memory,chip_enable;
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inout [15:0] pixel_color;
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inout [15:0] pixel_color;
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output [15:0] addr;
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output [15:0] addr;
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//wires
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//wires
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wire blank,pixel_clk,red_in,blue_in,green_in,clk_5M;
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wire blank,pixel_clk,red_in,blue_in,green_in,clk_5M;
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wire [10:0] hcounter;
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wire [10:0] hcounter;
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wire [10:0] vcounter;
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wire [10:0] vcounter;
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wire read_fifo,write_fifo;
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wire read_fifo,write_fifo;
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wire clk_2M,count;
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wire clk_2M,count;
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wire [15:0] pixel_set;
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wire [15:0] pixel_set;
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assign chip_enable = 0;
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assign chip_enable = 0;
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clk_divider clk1(clk, pixel_clk);
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clk_divider clk1(clk, pixel_clk);
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clk_divider #(.NDIV(10),.NBIT(4)) clk2(pixel_clk,clk_5M);
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clk_divider #(.NDIV(10),.NBIT(4)) clk2(pixel_clk,clk_5M);
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clk_divider #(.NDIV(20),.NBIT(5)) clk3(pixel_clk,clk_2M);
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clk_divider #(.NDIV(20),.NBIT(5)) clk3(pixel_clk,clk_2M);
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vga_controller vga1(reset,pixel_clk,h_sync,v_sync,hcounter,vcounter,blank);
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vga_controller vga1(reset,pixel_clk,h_sync,v_sync,hcounter,vcounter,blank);
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fifo_generator_v4_3 fifo1(
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fifo_generator_v4_3 fifo1(
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clk_2M,
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clk_2M,
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clk_5M,
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clk_5M,
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read_fifo,
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read_fifo,
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reset,
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reset,
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pixel_clk,
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pixel_clk,
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write_fifo,
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write_fifo,
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pixel_set,
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pixel_set,
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fifo_empty,
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fifo_empty,
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fifo_full);
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fifo_full);
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color_fsm vga2(reset,pixel_clk,clk_2M,pixel_set,fifo_full,fifo_empty,hcounter,vcounter,red_in,green_in,blue_in,read_fifo,write_fifo,write_memory,read_memory,count);
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color_fsm vga2(reset,pixel_clk,clk_2M,pixel_set,fifo_full,fifo_empty,hcounter,vcounter,red_in,green_in,blue_in,read_fifo,write_fifo,write_memory,read_memory,count);
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vga_display vga3(reset,pixel_clk,blank,red_in,blue_in,green_in,hcounter,vcounter,red_out,green_out,blue_out,count);
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vga_display vga3(reset,pixel_clk,blank,red_in,blue_in,green_in,hcounter,vcounter,red_out,green_out,blue_out,count);
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generate_add add1(clk_2M,addr,pixel_color);
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generate_add add1(clk_2M,addr,pixel_color);
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endmodule
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endmodule
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