/*******************************************************************************
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/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used *
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* This file is owned and controlled by Xilinx and must be used *
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* solely for design, simulation, implementation and creation of *
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* solely for design, simulation, implementation and creation of *
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* design files limited to Xilinx devices or technologies. Use *
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* design files limited to Xilinx devices or technologies. Use *
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* with non-Xilinx devices or technologies is expressly prohibited *
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* with non-Xilinx devices or technologies is expressly prohibited *
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* and immediately terminates your license. *
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* and immediately terminates your license. *
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* *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
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* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
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* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
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* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
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* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
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* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
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* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
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* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
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* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* Xilinx products are not intended for use in life support *
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* appliances, devices, or systems. Use in such applications are *
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* appliances, devices, or systems. Use in such applications are *
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* expressly prohibited. *
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* expressly prohibited. *
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* *
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* *
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* (c) Copyright 1995-2007 Xilinx, Inc. *
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* (c) Copyright 1995-2007 Xilinx, Inc. *
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* All rights reserved. *
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* All rights reserved. *
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*******************************************************************************/
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*******************************************************************************/
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// The synthesis directives "translate_off/translate_on" specified below are
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// The synthesis directives "translate_off/translate_on" specified below are
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// supported by Xilinx, Mentor Graphics and Synplicity synthesis
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// supported by Xilinx, Mentor Graphics and Synplicity synthesis
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// tools. Ensure they are correct for your synthesis tool(s).
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// tools. Ensure they are correct for your synthesis tool(s).
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// You must compile the wrapper file fifo_generator_v4_3.v when simulating
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// You must compile the wrapper file fifo_generator_v4_3.v when simulating
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// the core, fifo_generator_v4_3. When compiling the wrapper file, be sure to
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// the core, fifo_generator_v4_3. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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// instructions, please refer to the "CORE Generator Help".
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module fifo_generator_v4_3(
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module fifo_generator_v4_3(
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clk,
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clk,
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din,
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din,
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rd_en,
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rd_en,
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rst,
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rst,
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wr_en,
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wr_en,
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dout,
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dout,
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empty,
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empty,
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full);
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full);
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input clk;
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input clk;
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input [15 : 0] din;
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input [15 : 0] din;
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input rd_en;
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input rd_en;
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input rst;
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input rst;
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input wr_en;
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input wr_en;
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output [15 : 0] dout;
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output [15 : 0] dout;
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output empty;
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output empty;
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output full;
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output full;
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// synthesis translate_off
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// synthesis translate_off
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FIFO_GENERATOR_V4_3 #(
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FIFO_GENERATOR_V4_3 #(
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.C_COMMON_CLOCK(1),
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.C_COMMON_CLOCK(1),
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.C_COUNT_TYPE(0),
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.C_COUNT_TYPE(0),
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.C_DATA_COUNT_WIDTH(14),
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.C_DATA_COUNT_WIDTH(14),
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.C_DEFAULT_VALUE("BlankString"),
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.C_DEFAULT_VALUE("BlankString"),
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.C_DIN_WIDTH(16),
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.C_DIN_WIDTH(16),
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.C_DOUT_RST_VAL("0"),
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.C_DOUT_RST_VAL("0"),
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.C_DOUT_WIDTH(16),
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.C_DOUT_WIDTH(16),
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.C_ENABLE_RLOCS(0),
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.C_ENABLE_RLOCS(0),
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.C_FAMILY("spartan3"),
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.C_FAMILY("spartan3"),
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.C_FULL_FLAGS_RST_VAL(1),
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.C_FULL_FLAGS_RST_VAL(1),
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.C_HAS_ALMOST_EMPTY(0),
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.C_HAS_ALMOST_EMPTY(0),
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.C_HAS_ALMOST_FULL(0),
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.C_HAS_ALMOST_FULL(0),
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.C_HAS_BACKUP(0),
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.C_HAS_BACKUP(0),
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.C_HAS_DATA_COUNT(0),
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.C_HAS_DATA_COUNT(0),
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.C_HAS_INT_CLK(0),
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.C_HAS_INT_CLK(0),
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.C_HAS_MEMINIT_FILE(0),
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.C_HAS_MEMINIT_FILE(0),
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.C_HAS_OVERFLOW(0),
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.C_HAS_OVERFLOW(0),
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.C_HAS_RD_DATA_COUNT(0),
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.C_HAS_RD_DATA_COUNT(0),
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.C_HAS_RD_RST(0),
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.C_HAS_RD_RST(0),
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.C_HAS_RST(1),
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.C_HAS_RST(1),
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.C_HAS_SRST(0),
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.C_HAS_SRST(0),
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.C_HAS_UNDERFLOW(0),
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.C_HAS_UNDERFLOW(0),
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.C_HAS_VALID(0),
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.C_HAS_VALID(0),
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.C_HAS_WR_ACK(0),
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.C_HAS_WR_ACK(0),
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.C_HAS_WR_DATA_COUNT(0),
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.C_HAS_WR_DATA_COUNT(0),
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.C_HAS_WR_RST(0),
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.C_HAS_WR_RST(0),
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.C_IMPLEMENTATION_TYPE(0),
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.C_IMPLEMENTATION_TYPE(0),
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.C_INIT_WR_PNTR_VAL(0),
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.C_INIT_WR_PNTR_VAL(0),
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.C_MEMORY_TYPE(1),
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.C_MEMORY_TYPE(1),
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.C_MIF_FILE_NAME("BlankString"),
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.C_MIF_FILE_NAME("BlankString"),
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.C_MSGON_VAL(1),
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.C_MSGON_VAL(1),
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.C_OPTIMIZATION_MODE(0),
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.C_OPTIMIZATION_MODE(0),
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.C_OVERFLOW_LOW(0),
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.C_OVERFLOW_LOW(0),
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.C_PRELOAD_LATENCY(1),
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.C_PRELOAD_LATENCY(1),
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.C_PRELOAD_REGS(0),
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.C_PRELOAD_REGS(0),
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.C_PRIM_FIFO_TYPE("8kx4"),
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.C_PRIM_FIFO_TYPE("8kx4"),
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.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
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.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
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.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
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.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
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.C_PROG_EMPTY_TYPE(0),
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.C_PROG_EMPTY_TYPE(0),
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.C_PROG_FULL_THRESH_ASSERT_VAL(16382),
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.C_PROG_FULL_THRESH_ASSERT_VAL(16382),
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.C_PROG_FULL_THRESH_NEGATE_VAL(16381),
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.C_PROG_FULL_THRESH_NEGATE_VAL(16381),
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.C_PROG_FULL_TYPE(0),
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.C_PROG_FULL_TYPE(0),
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.C_RD_DATA_COUNT_WIDTH(14),
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.C_RD_DATA_COUNT_WIDTH(14),
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.C_RD_DEPTH(16384),
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.C_RD_DEPTH(16384),
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.C_RD_FREQ(1),
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.C_RD_FREQ(1),
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.C_RD_PNTR_WIDTH(14),
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.C_RD_PNTR_WIDTH(14),
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.C_UNDERFLOW_LOW(0),
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.C_UNDERFLOW_LOW(0),
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.C_USE_DOUT_RST(1),
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.C_USE_DOUT_RST(1),
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.C_USE_ECC(0),
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.C_USE_ECC(0),
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.C_USE_EMBEDDED_REG(0),
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.C_USE_EMBEDDED_REG(0),
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.C_USE_FIFO16_FLAGS(0),
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.C_USE_FIFO16_FLAGS(0),
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.C_USE_FWFT_DATA_COUNT(0),
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.C_USE_FWFT_DATA_COUNT(0),
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.C_VALID_LOW(0),
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.C_VALID_LOW(0),
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.C_WR_ACK_LOW(0),
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.C_WR_ACK_LOW(0),
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.C_WR_DATA_COUNT_WIDTH(14),
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.C_WR_DATA_COUNT_WIDTH(14),
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.C_WR_DEPTH(16384),
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.C_WR_DEPTH(16384),
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.C_WR_FREQ(1),
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.C_WR_FREQ(1),
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.C_WR_PNTR_WIDTH(14),
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.C_WR_PNTR_WIDTH(14),
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.C_WR_RESPONSE_LATENCY(1))
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.C_WR_RESPONSE_LATENCY(1))
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inst (
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inst (
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.CLK(clk),
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.CLK(clk),
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.DIN(din),
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.DIN(din),
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.RD_EN(rd_en),
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.RD_EN(rd_en),
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.RST(rst),
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.RST(rst),
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.WR_EN(wr_en),
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.WR_EN(wr_en),
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.DOUT(dout),
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.DOUT(dout),
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.EMPTY(empty),
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.EMPTY(empty),
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.FULL(full),
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.FULL(full),
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.INT_CLK(),
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.INT_CLK(),
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.BACKUP(),
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.BACKUP(),
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.BACKUP_MARKER(),
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.BACKUP_MARKER(),
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.PROG_EMPTY_THRESH(),
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.PROG_EMPTY_THRESH(),
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.PROG_EMPTY_THRESH_ASSERT(),
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.PROG_EMPTY_THRESH_ASSERT(),
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.PROG_EMPTY_THRESH_NEGATE(),
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.PROG_EMPTY_THRESH_NEGATE(),
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.PROG_FULL_THRESH(),
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.PROG_FULL_THRESH(),
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.PROG_FULL_THRESH_ASSERT(),
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.PROG_FULL_THRESH_ASSERT(),
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.PROG_FULL_THRESH_NEGATE(),
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.PROG_FULL_THRESH_NEGATE(),
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.RD_CLK(),
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.RD_CLK(),
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.RD_RST(),
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.RD_RST(),
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.SRST(),
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.SRST(),
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.WR_CLK(),
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.WR_CLK(),
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.WR_RST(),
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.WR_RST(),
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.ALMOST_EMPTY(),
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.ALMOST_EMPTY(),
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.ALMOST_FULL(),
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.ALMOST_FULL(),
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.DATA_COUNT(),
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.DATA_COUNT(),
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.OVERFLOW(),
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.OVERFLOW(),
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.PROG_EMPTY(),
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.PROG_EMPTY(),
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.PROG_FULL(),
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.PROG_FULL(),
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.VALID(),
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.VALID(),
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.RD_DATA_COUNT(),
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.RD_DATA_COUNT(),
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.UNDERFLOW(),
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.UNDERFLOW(),
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.WR_ACK(),
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.WR_ACK(),
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.WR_DATA_COUNT(),
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.WR_DATA_COUNT(),
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.SBITERR(),
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.SBITERR(),
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.DBITERR());
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.DBITERR());
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// synthesis translate_on
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// synthesis translate_on
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endmodule
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endmodule
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