/*******************************************************************************
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/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used *
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* This file is owned and controlled by Xilinx and must be used *
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* solely for design, simulation, implementation and creation of *
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* solely for design, simulation, implementation and creation of *
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* design files limited to Xilinx devices or technologies. Use *
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* design files limited to Xilinx devices or technologies. Use *
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* with non-Xilinx devices or technologies is expressly prohibited *
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* with non-Xilinx devices or technologies is expressly prohibited *
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* and immediately terminates your license. *
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* and immediately terminates your license. *
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* *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
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* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
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* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
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* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* appliances, devices, or systems. Use in such applications are *
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* (c) Copyright 1995-2007 Xilinx, Inc. *
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* (c) Copyright 1995-2007 Xilinx, Inc. *
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* All rights reserved. *
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* All rights reserved. *
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*******************************************************************************/
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*******************************************************************************/
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// The synthesis directives "translate_off/translate_on" specified below are
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// The synthesis directives "translate_off/translate_on" specified below are
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// supported by Xilinx, Mentor Graphics and Synplicity synthesis
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// supported by Xilinx, Mentor Graphics and Synplicity synthesis
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// tools. Ensure they are correct for your synthesis tool(s).
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// tools. Ensure they are correct for your synthesis tool(s).
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// You must compile the wrapper file blk_mem_gen_v2_7.v when simulating
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// You must compile the wrapper file blk_mem_gen_v2_7.v when simulating
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// the core, blk_mem_gen_v2_7. When compiling the wrapper file, be sure to
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// the core, blk_mem_gen_v2_7. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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// instructions, please refer to the "CORE Generator Help".
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module blk_mem_gen_v2_7(
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module blk_mem_gen_v2_7(
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clka,
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clka,
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dina,
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dina,
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addra,
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addra,
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ena,
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ena,
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wea,
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wea,
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douta,
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douta,
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clkb,
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clkb,
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dinb,
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dinb,
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addrb,
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addrb,
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enb,
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enb,
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web,
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web,
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doutb);
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doutb);
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input clka;
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input clka;
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input [15 : 0] dina;
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input [15 : 0] dina;
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input [15 : 0] addra;
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input [15 : 0] addra;
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input ena;
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input ena;
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input [0 : 0] wea;
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input [0 : 0] wea;
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output [15 : 0] douta;
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output [15 : 0] douta;
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input clkb;
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input clkb;
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input [15 : 0] dinb;
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input [15 : 0] dinb;
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input [15 : 0] addrb;
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input [15 : 0] addrb;
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input enb;
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input enb;
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input [0 : 0] web;
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input [0 : 0] web;
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output [15 : 0] doutb;
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output [15 : 0] doutb;
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// synthesis translate_off
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// synthesis translate_off
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BLK_MEM_GEN_V2_7 #(
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BLK_MEM_GEN_V2_7 #(
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.C_ADDRA_WIDTH(16),
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.C_ADDRA_WIDTH(16),
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.C_ADDRB_WIDTH(16),
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.C_ADDRB_WIDTH(16),
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.C_ALGORITHM(1),
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.C_ALGORITHM(1),
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.C_BYTE_SIZE(9),
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.C_BYTE_SIZE(9),
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.C_COMMON_CLK(0),
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.C_COMMON_CLK(0),
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.C_DEFAULT_DATA("0"),
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.C_DEFAULT_DATA("0"),
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.C_DISABLE_WARN_BHV_COLL(0),
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.C_DISABLE_WARN_BHV_COLL(0),
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.C_DISABLE_WARN_BHV_RANGE(0),
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.C_DISABLE_WARN_BHV_RANGE(0),
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.C_FAMILY("spartan3"),
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.C_FAMILY("spartan3"),
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.C_HAS_ENA(1),
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.C_HAS_ENA(1),
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.C_HAS_ENB(1),
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.C_HAS_ENB(1),
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.C_HAS_MEM_OUTPUT_REGS_A(0),
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.C_HAS_MEM_OUTPUT_REGS_A(0),
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.C_HAS_MEM_OUTPUT_REGS_B(0),
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.C_HAS_MEM_OUTPUT_REGS_B(0),
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.C_HAS_MUX_OUTPUT_REGS_A(0),
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.C_HAS_MUX_OUTPUT_REGS_A(0),
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.C_HAS_MUX_OUTPUT_REGS_B(0),
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.C_HAS_MUX_OUTPUT_REGS_B(0),
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.C_HAS_REGCEA(0),
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.C_HAS_REGCEA(0),
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.C_HAS_REGCEB(0),
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.C_HAS_REGCEB(0),
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.C_HAS_SSRA(0),
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.C_HAS_SSRA(0),
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.C_HAS_SSRB(0),
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.C_HAS_SSRB(0),
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.C_INIT_FILE_NAME("blk_mem_gen_v2_7.mif"),
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.C_INIT_FILE_NAME("blk_mem_gen_v2_7.mif"),
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.C_LOAD_INIT_FILE(1),
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.C_LOAD_INIT_FILE(1),
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.C_MEM_TYPE(2),
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.C_MEM_TYPE(2),
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.C_MUX_PIPELINE_STAGES(0),
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.C_MUX_PIPELINE_STAGES(0),
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.C_PRIM_TYPE(1),
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.C_PRIM_TYPE(1),
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.C_READ_DEPTH_A(40000),
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.C_READ_DEPTH_A(40000),
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.C_READ_DEPTH_B(40000),
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.C_READ_DEPTH_B(40000),
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.C_READ_WIDTH_A(16),
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.C_READ_WIDTH_A(16),
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.C_READ_WIDTH_B(16),
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.C_READ_WIDTH_B(16),
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.C_SIM_COLLISION_CHECK("ALL"),
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.C_SIM_COLLISION_CHECK("ALL"),
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.C_SINITA_VAL("0"),
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.C_SINITA_VAL("0"),
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.C_SINITB_VAL("0"),
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.C_SINITB_VAL("0"),
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.C_USE_BYTE_WEA(0),
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.C_USE_BYTE_WEA(0),
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.C_USE_BYTE_WEB(0),
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.C_USE_BYTE_WEB(0),
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.C_USE_DEFAULT_DATA(0),
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.C_USE_DEFAULT_DATA(0),
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.C_USE_ECC(0),
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.C_USE_ECC(0),
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.C_USE_RAMB16BWER_RST_BHV(0),
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.C_USE_RAMB16BWER_RST_BHV(0),
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.C_WEA_WIDTH(1),
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.C_WEA_WIDTH(1),
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.C_WEB_WIDTH(1),
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.C_WEB_WIDTH(1),
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.C_WRITE_DEPTH_A(40000),
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.C_WRITE_DEPTH_A(40000),
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.C_WRITE_DEPTH_B(40000),
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.C_WRITE_DEPTH_B(40000),
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.C_WRITE_MODE_A("WRITE_FIRST"),
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.C_WRITE_MODE_A("WRITE_FIRST"),
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.C_WRITE_MODE_B("WRITE_FIRST"),
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.C_WRITE_MODE_B("WRITE_FIRST"),
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.C_WRITE_WIDTH_A(16),
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.C_WRITE_WIDTH_A(16),
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.C_WRITE_WIDTH_B(16),
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.C_WRITE_WIDTH_B(16),
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.C_XDEVICEFAMILY("spartan3"))
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.C_XDEVICEFAMILY("spartan3"))
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inst (
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inst (
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.CLKA(clka),
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.CLKA(clka),
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.DINA(dina),
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.DINA(dina),
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.ADDRA(addra),
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.ADDRA(addra),
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.ENA(ena),
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.ENA(ena),
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.WEA(wea),
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.WEA(wea),
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.DOUTA(douta),
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.DOUTA(douta),
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.CLKB(clkb),
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.CLKB(clkb),
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.DINB(dinb),
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.DINB(dinb),
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.ADDRB(addrb),
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.ADDRB(addrb),
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.ENB(enb),
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.ENB(enb),
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.WEB(web),
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.WEB(web),
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.DOUTB(doutb),
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.DOUTB(doutb),
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.REGCEA(),
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.REGCEA(),
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.SSRA(),
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.SSRA(),
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.REGCEB(),
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.REGCEB(),
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.SSRB(),
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.SSRB(),
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.DBITERR(),
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.DBITERR(),
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.SBITERR());
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.SBITERR());
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// synthesis translate_on
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// synthesis translate_on
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endmodule
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endmodule
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