`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 00:32:52 11/20/2008
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// Create Date: 00:32:52 11/20/2008
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// Design Name:
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// Design Name:
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// Module Name: color_fsm
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// Module Name: color_fsm
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module color_fsm(reset,clk_20MHz,clk_2MHz,pixel_set_rgb,fifo_full,fifo_empty,
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module color_fsm(reset,clk_20MHz,clk_2MHz,pixel_set_rgb,fifo_full,fifo_empty,
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hcount,vcount,red_in,green_in,blue_in,
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hcount,vcount,red_in,green_in,blue_in,
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read_fifo,write_fifo,write_memory,read_memory,count);
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read_fifo,write_fifo,write_memory,read_memory,count);
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//Inputs
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//Inputs
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input clk_20MHz,clk_2MHz,reset,fifo_full,fifo_empty;
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input clk_20MHz,clk_2MHz,reset,fifo_full,fifo_empty;
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input [15:0] pixel_set_rgb;
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input [15:0] pixel_set_rgb;
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input [10:0] hcount;
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input [10:0] hcount;
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input [10:0] vcount;
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input [10:0] vcount;
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//Outputs
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//Outputs
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output red_in,green_in,blue_in,read_fifo,write_fifo;
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output red_in,green_in,blue_in,read_fifo,write_fifo;
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output write_memory, read_memory,count;
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output write_memory, read_memory,count;
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//regs
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//regs
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reg red_in, green_in, blue_in,read_fifo,write_fifo,read_memory,write_memory;
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reg red_in, green_in, blue_in,read_fifo,write_fifo,read_memory,write_memory;
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reg [2:0] pixel_state = 0;
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reg [2:0] pixel_state = 0;
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reg count = 0;
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reg count = 0;
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//parameters
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//parameters
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parameter [2:0] pixel_1 = 0;
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parameter [2:0] pixel_1 = 0;
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parameter [2:0] pixel_2 = 1;
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parameter [2:0] pixel_2 = 1;
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parameter [2:0] pixel_3 = 2;
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parameter [2:0] pixel_3 = 2;
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parameter [2:0] pixel_4 = 3;
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parameter [2:0] pixel_4 = 3;
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parameter [2:0] pixel_5 = 4;
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parameter [2:0] pixel_5 = 4;
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parameter [8:0] xpos_start = 192;
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parameter [8:0] xpos_start = 192;
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parameter [8:0] ypos_start = 48;
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parameter [8:0] ypos_start = 48;
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parameter [8:0] xpos_end = 448;
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parameter [8:0] xpos_end = 448;
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parameter [8:0] ypos_end = 432;
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parameter [8:0] ypos_end = 432;
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always @ (clk_2MHz)
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always @ (clk_2MHz)
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begin
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begin
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if(count == 0) begin
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if(count == 0) begin
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write_memory <= 0;
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write_memory <= 0;
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read_memory <= 1;
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read_memory <= 1;
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if(hcount == 649 && vcount == 479)
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if(hcount == 649 && vcount == 479)
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count <= 1;
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count <= 1;
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end
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end
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else if(count == 1) begin
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else if(count == 1) begin
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read_memory <= 0;
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read_memory <= 0;
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write_memory <= 1;
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write_memory <= 1;
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end
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end
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end
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end
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always @ (posedge clk_20MHz)
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always @ (posedge clk_20MHz)
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begin
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begin
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if(count == 1) begin
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if(count == 1) begin
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if(reset) begin
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if(reset) begin
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pixel_state <= pixel_1;
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pixel_state <= pixel_1;
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end
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end
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else if(vcount >= ypos_start && vcount < ypos_end) begin
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else if(vcount >= ypos_start && vcount < ypos_end) begin
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if(hcount >= xpos_start && hcount < xpos_end) begin
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if(hcount >= xpos_start && hcount < xpos_end) begin
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case(pixel_state)
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case(pixel_state)
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pixel_1 :
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pixel_1 :
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begin
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begin
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red_in <= pixel_set_rgb[2];
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red_in <= pixel_set_rgb[2];
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green_in <= pixel_set_rgb[1];
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green_in <= pixel_set_rgb[1];
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blue_in <= pixel_set_rgb[0];
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blue_in <= pixel_set_rgb[0];
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pixel_state <= pixel_2;
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pixel_state <= pixel_2;
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end
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end
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pixel_2 :
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pixel_2 :
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begin
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begin
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red_in <= pixel_set_rgb[5];
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red_in <= pixel_set_rgb[5];
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green_in <= pixel_set_rgb[4];
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green_in <= pixel_set_rgb[4];
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blue_in <= pixel_set_rgb[3];
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blue_in <= pixel_set_rgb[3];
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pixel_state <= pixel_3;
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pixel_state <= pixel_3;
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end
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end
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pixel_3 :
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pixel_3 :
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begin
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begin
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red_in <= pixel_set_rgb[8];
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red_in <= pixel_set_rgb[8];
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green_in <= pixel_set_rgb[7];
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green_in <= pixel_set_rgb[7];
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blue_in <= pixel_set_rgb[6];
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blue_in <= pixel_set_rgb[6];
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pixel_state <= pixel_4;
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pixel_state <= pixel_4;
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end
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end
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pixel_4 :
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pixel_4 :
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begin
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begin
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red_in <= pixel_set_rgb[11];
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red_in <= pixel_set_rgb[11];
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green_in <= pixel_set_rgb[10];
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green_in <= pixel_set_rgb[10];
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blue_in <= pixel_set_rgb[9];
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blue_in <= pixel_set_rgb[9];
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pixel_state <= pixel_5;
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pixel_state <= pixel_5;
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end
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end
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pixel_5 :
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pixel_5 :
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begin
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begin
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red_in <= pixel_set_rgb[14];
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red_in <= pixel_set_rgb[14];
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green_in <= pixel_set_rgb[13];
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green_in <= pixel_set_rgb[13];
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blue_in <= pixel_set_rgb[12];
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blue_in <= pixel_set_rgb[12];
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pixel_state <= pixel_1;
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pixel_state <= pixel_1;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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if(fifo_empty == 1)
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if(fifo_empty == 1)
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read_fifo <= 0;
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read_fifo <= 0;
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else
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else
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read_fifo <= 1;
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read_fifo <= 1;
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if(fifo_full == 1)
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if(fifo_full == 1)
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write_fifo <= 0;
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write_fifo <= 0;
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else
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else
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write_fifo <= 1;
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write_fifo <= 1;
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end
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end
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end
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end
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endmodule
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endmodule
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