Release 10.1 par K.31 (nt)
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Release 10.1 par K.31 (nt)
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Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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ECE-PHO117-40:: Thu Nov 20 21:07:34 2008
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ECE-PHO117-40:: Thu Nov 20 21:07:34 2008
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par -w -intstyle ise -ol std -t 1 test_memory_map.ncd test_memory.ncd
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par -w -intstyle ise -ol std -t 1 test_memory_map.ncd test_memory.ncd
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test_memory.pcf
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test_memory.pcf
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Constraints file: test_memory.pcf.
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Constraints file: test_memory.pcf.
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Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx\10.1\ISE.
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Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx\10.1\ISE.
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"test_memory" is an NCD, version 3.2, device xc3s200, package ft256, speed -4
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"test_memory" is an NCD, version 3.2, device xc3s200, package ft256, speed -4
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
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internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
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the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
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the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
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balance between the fastest runtime and best performance, set the effort level to "med".
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balance between the fastest runtime and best performance, set the effort level to "med".
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Device speed data version: "PRODUCTION 1.39 2008-01-09".
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Device speed data version: "PRODUCTION 1.39 2008-01-09".
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Device Utilization Summary:
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Device Utilization Summary:
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Number of External IOBs 10 out of 173 5%
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Number of External IOBs 10 out of 173 5%
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Number of LOCed IOBs 10 out of 10 100%
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Number of LOCed IOBs 10 out of 10 100%
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Number of RAMB16s 1 out of 12 8%
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Number of RAMB16s 1 out of 12 8%
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Overall effort level (-ol): Standard
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Overall effort level (-ol): Standard
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Placer effort level (-pl): High
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Placer effort level (-pl): High
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Placer cost table entry (-t): 1
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Placer cost table entry (-t): 1
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Router effort level (-rl): Standard
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Router effort level (-rl): Standard
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WARNING:Par:288 - The signal clk_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal clk_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
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Starting Placer
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Starting Placer
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Phase 1.1
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Phase 1.1
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Phase 1.1 (Checksum:989695) REAL time: 0 secs
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Phase 1.1 (Checksum:989695) REAL time: 0 secs
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Phase 2.7
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Phase 2.7
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Phase 2.7 (Checksum:1312cfe) REAL time: 1 secs
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Phase 2.7 (Checksum:1312cfe) REAL time: 1 secs
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Phase 3.31
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Phase 3.31
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Phase 3.31 (Checksum:1c9c37d) REAL time: 1 secs
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Phase 3.31 (Checksum:1c9c37d) REAL time: 1 secs
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Phase 4.2
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Phase 4.2
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Phase 4.2 (Checksum:26259fc) REAL time: 1 secs
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Phase 4.2 (Checksum:26259fc) REAL time: 1 secs
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Phase 5.8
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Phase 5.8
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............
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............
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Phase 5.8 (Checksum:98b7e5) REAL time: 1 secs
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Phase 5.8 (Checksum:98b7e5) REAL time: 1 secs
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Phase 6.5
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Phase 6.5
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Phase 6.5 (Checksum:39386fa) REAL time: 1 secs
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Phase 6.5 (Checksum:39386fa) REAL time: 1 secs
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Phase 7.18
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Phase 7.18
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Phase 7.18 (Checksum:42c1d79) REAL time: 1 secs
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Phase 7.18 (Checksum:42c1d79) REAL time: 1 secs
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Phase 8.5
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Phase 8.5
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Phase 8.5 (Checksum:4c4b3f8) REAL time: 1 secs
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Phase 8.5 (Checksum:4c4b3f8) REAL time: 1 secs
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REAL time consumed by placer: 1 secs
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REAL time consumed by placer: 1 secs
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CPU time consumed by placer: 0 secs
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CPU time consumed by placer: 0 secs
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Writing design to file test_memory.ncd
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Writing design to file test_memory.ncd
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Total REAL time to Placer completion: 1 secs
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Total REAL time to Placer completion: 1 secs
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Total CPU time to Placer completion: 0 secs
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Total CPU time to Placer completion: 0 secs
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Starting Router
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Starting Router
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Phase 1: 47 unrouted; REAL time: 4 secs
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Phase 1: 47 unrouted; REAL time: 4 secs
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Phase 2: 39 unrouted; REAL time: 4 secs
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Phase 2: 39 unrouted; REAL time: 4 secs
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Phase 3: 0 unrouted; REAL time: 4 secs
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Phase 3: 0 unrouted; REAL time: 4 secs
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Phase 4: 0 unrouted; (0) REAL time: 4 secs
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Phase 4: 0 unrouted; (0) REAL time: 4 secs
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Phase 5: 0 unrouted; (0) REAL time: 4 secs
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Phase 5: 0 unrouted; (0) REAL time: 4 secs
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Phase 6: 0 unrouted; (0) REAL time: 4 secs
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Phase 6: 0 unrouted; (0) REAL time: 4 secs
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Total REAL time to Router completion: 4 secs
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Total REAL time to Router completion: 4 secs
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Total CPU time to Router completion: 1 secs
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Total CPU time to Router completion: 1 secs
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Partition Implementation Status
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Partition Implementation Status
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-------------------------------
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-------------------------------
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No Partitions were found in this design.
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No Partitions were found in this design.
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-------------------------------
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-------------------------------
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Generating "PAR" statistics.
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Generating "PAR" statistics.
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Timing Score: 0
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Timing Score: 0
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Generating Pad Report.
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Generating Pad Report.
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All signals are completely routed.
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All signals are completely routed.
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WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
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WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
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Total REAL time to PAR completion: 16 secs
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Total REAL time to PAR completion: 16 secs
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Total CPU time to PAR completion: 3 secs
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Total CPU time to PAR completion: 3 secs
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Peak Memory Usage: 100 MB
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Peak Memory Usage: 100 MB
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Placement: Completed - No errors found.
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of error messages: 0
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Number of warning messages: 4
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Number of warning messages: 4
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Number of info messages: 1
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Number of info messages: 1
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Writing design to file test_memory.ncd
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Writing design to file test_memory.ncd
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PAR done!
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PAR done!
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