module virtual_jtag_adda_fifo(clk,wr_en,data_in);
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module virtual_jtag_adda_fifo(clk,wr_en,data_in);
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parameter data_width = 32,
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parameter data_width = 32,
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fifo_depth = 256,
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fifo_depth = 256,
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addr_width = 8,
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addr_width = 8,
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al_full_val = 255,
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al_full_val = 255,
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al_empt_val = 0;
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al_empt_val = 0;
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input clk;
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input clk;
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input wr_en;
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input wr_en;
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input [data_width-1:0] data_in;
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input [data_width-1:0] data_in;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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reg tdo;
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reg tdo;
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reg [addr_width-1:0] usedw_instr_reg;
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reg [addr_width-1:0] usedw_instr_reg;
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reg reset_instr_reg;
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reg reset_instr_reg;
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reg [data_width-1:0] read_instr_reg;
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reg [data_width-1:0] read_instr_reg;
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reg bypass_reg;
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reg bypass_reg;
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wire [1:0] ir_in;
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wire [1:0] ir_in;
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wire usedw_instr = ~ir_in[1] & ir_in[0]; // 1
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wire usedw_instr = ~ir_in[1] & ir_in[0]; // 1
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wire reset_instr = ir_in[1] & ~ir_in[0]; // 2
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wire reset_instr = ir_in[1] & ~ir_in[0]; // 2
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wire read_instr = ir_in[1] & ir_in[0]; // 3
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wire read_instr = ir_in[1] & ir_in[0]; // 3
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wire reset = reset_instr && e1dr;
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wire reset = reset_instr && e1dr;
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wire [addr_width-1:0] usedw;
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wire [addr_width-1:0] usedw;
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wire [data_width-1:0] data_out;
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wire [data_width-1:0] data_out;
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wire full;
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wire full;
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wire al_full;
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wire al_full;
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reg read_instr_d1;
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reg read_instr_d1;
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reg read_instr_d2;
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reg read_instr_d2;
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reg read_instr_d3;
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reg read_instr_d3;
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wire rd_en = read_instr_d2 & !read_instr_d3;
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wire rd_en = read_instr_d2 & !read_instr_d3;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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read_instr_d1 <= 1'b0;
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read_instr_d1 <= 1'b0;
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read_instr_d2 <= 1'b0;
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read_instr_d2 <= 1'b0;
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read_instr_d3 <= 1'b0;
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read_instr_d3 <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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read_instr_d1 <= read_instr;
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read_instr_d1 <= read_instr;
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read_instr_d2 <= read_instr_d1;
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read_instr_d2 <= read_instr_d1;
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read_instr_d3 <= read_instr_d2;
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read_instr_d3 <= read_instr_d2;
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end
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end
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end
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end
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scfifo jtag_fifo (
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scfifo jtag_fifo (
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.aclr (reset),
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.aclr (reset),
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.clock (clk),
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.clock (clk),
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.wrreq (wr_en & !al_full),
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.wrreq (wr_en & !al_full),
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.data (data_in),
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.data (data_in),
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.rdreq (rd_en),
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.rdreq (rd_en),
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.q (data_out),
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.q (data_out),
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.full (full),
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.full (full),
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.almost_full (al_full),
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.almost_full (al_full),
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.empty (),
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.empty (),
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.almost_empty (),
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.almost_empty (),
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.usedw (usedw),
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.usedw (usedw),
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.sclr ());
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.sclr ());
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defparam
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defparam
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jtag_fifo.lpm_width = data_width,
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jtag_fifo.lpm_width = data_width,
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jtag_fifo.lpm_numwords = fifo_depth,
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jtag_fifo.lpm_numwords = fifo_depth,
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jtag_fifo.lpm_widthu = addr_width,
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jtag_fifo.lpm_widthu = addr_width,
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jtag_fifo.intended_device_family = "Stratix II",
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jtag_fifo.intended_device_family = "Stratix II",
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jtag_fifo.almost_full_value = al_full_val,
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jtag_fifo.almost_full_value = al_full_val,
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jtag_fifo.almost_empty_value = al_empt_val,
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jtag_fifo.almost_empty_value = al_empt_val,
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jtag_fifo.lpm_type = "scfifo",
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jtag_fifo.lpm_type = "scfifo",
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jtag_fifo.lpm_showahead = "OFF",
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jtag_fifo.lpm_showahead = "OFF",
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jtag_fifo.overflow_checking = "ON",
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jtag_fifo.overflow_checking = "ON",
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jtag_fifo.underflow_checking = "ON",
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jtag_fifo.underflow_checking = "ON",
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jtag_fifo.use_eab = "ON",
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jtag_fifo.use_eab = "ON",
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jtag_fifo.add_ram_output_register = "ON";
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jtag_fifo.add_ram_output_register = "ON";
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/* usedw_instr Instruction Handler */
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/* usedw_instr Instruction Handler */
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always @ (posedge tck)
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always @ (posedge tck)
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if ( usedw_instr && cdr )
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if ( usedw_instr && cdr )
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usedw_instr_reg <= usedw;
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usedw_instr_reg <= usedw;
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else if ( usedw_instr && sdr )
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else if ( usedw_instr && sdr )
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usedw_instr_reg <= {tdi, usedw_instr_reg[addr_width-1:1]};
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usedw_instr_reg <= {tdi, usedw_instr_reg[addr_width-1:1]};
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/* reset_instr Instruction Handler */
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/* reset_instr Instruction Handler */
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always @ (posedge tck)
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always @ (posedge tck)
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if ( reset_instr && sdr )
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if ( reset_instr && sdr )
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reset_instr_reg <= tdi;//{tdi, reset_instr_reg[data_width-1:1]};
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reset_instr_reg <= tdi;//{tdi, reset_instr_reg[data_width-1:1]};
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/* read_instr Instruction Handler */
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/* read_instr Instruction Handler */
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always @ (posedge tck)
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always @ (posedge tck)
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if ( read_instr && cdr )
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if ( read_instr && cdr )
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read_instr_reg <= data_out;
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read_instr_reg <= data_out;
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else if ( read_instr && sdr )
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else if ( read_instr && sdr )
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read_instr_reg <= {tdi, read_instr_reg[data_width-1:1]};
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read_instr_reg <= {tdi, read_instr_reg[data_width-1:1]};
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/* Bypass register */
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/* Bypass register */
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always @ (posedge tck)
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always @ (posedge tck)
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bypass_reg = tdi;
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bypass_reg = tdi;
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/* Node TDO Output */
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/* Node TDO Output */
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always @ ( usedw_instr, reset_instr, read_instr, usedw_instr_reg[0], reset_instr_reg/*[0]*/, read_instr_reg[0], bypass_reg )
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always @ ( usedw_instr, reset_instr, read_instr, usedw_instr_reg[0], reset_instr_reg/*[0]*/, read_instr_reg[0], bypass_reg )
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begin
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begin
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if (usedw_instr)
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if (usedw_instr)
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tdo <= usedw_instr_reg[0];
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tdo <= usedw_instr_reg[0];
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else if (reset_instr)
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else if (reset_instr)
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tdo <= reset_instr_reg/*[0]*/;
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tdo <= reset_instr_reg/*[0]*/;
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else if (read_instr)
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else if (read_instr)
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tdo <= read_instr_reg[0];
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tdo <= read_instr_reg[0];
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else
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else
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tdo <= bypass_reg; // Used to maintain the continuity of the scan chain.
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tdo <= bypass_reg; // Used to maintain the continuity of the scan chain.
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end
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end
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sld_virtual_jtag sld_virtual_jtag_component (
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sld_virtual_jtag sld_virtual_jtag_component (
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.ir_in (ir_in),
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.ir_in (ir_in),
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.ir_out (2'b0),
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.ir_out (2'b0),
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.tdo (tdo),
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.tdo (tdo),
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.tdi (tdi),
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.tdi (tdi),
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.tms (),
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.tms (),
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.tck (tck),
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.tck (tck),
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.virtual_state_cir (cir),
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.virtual_state_cir (cir),
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.virtual_state_pdr (pdr),
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.virtual_state_pdr (pdr),
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.virtual_state_uir (uir),
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.virtual_state_uir (uir),
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.virtual_state_sdr (sdr),
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.virtual_state_sdr (sdr),
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.virtual_state_cdr (cdr),
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.virtual_state_cdr (cdr),
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.virtual_state_udr (udr),
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.virtual_state_udr (udr),
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.virtual_state_e1dr (e1dr),
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.virtual_state_e1dr (e1dr),
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.virtual_state_e2dr (e2dr),
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.virtual_state_e2dr (e2dr),
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.jtag_state_rti (),
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.jtag_state_rti (),
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.jtag_state_e1dr (),
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.jtag_state_e1dr (),
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.jtag_state_e2dr (),
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.jtag_state_e2dr (),
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.jtag_state_pir (),
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.jtag_state_pir (),
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.jtag_state_tlr (),
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.jtag_state_tlr (),
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.jtag_state_sir (),
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.jtag_state_sir (),
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.jtag_state_cir (),
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.jtag_state_cir (),
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.jtag_state_uir (),
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.jtag_state_uir (),
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.jtag_state_pdr (),
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.jtag_state_pdr (),
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.jtag_state_sdrs (),
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.jtag_state_sdrs (),
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.jtag_state_sdr (),
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.jtag_state_sdr (),
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.jtag_state_cdr (),
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.jtag_state_cdr (),
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.jtag_state_udr (),
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.jtag_state_udr (),
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.jtag_state_sirs (),
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.jtag_state_sirs (),
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.jtag_state_e1ir (),
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.jtag_state_e1ir (),
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.jtag_state_e2ir ());
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.jtag_state_e2ir ());
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defparam
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defparam
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sld_virtual_jtag_component.sld_auto_instance_index = "NO",
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sld_virtual_jtag_component.sld_auto_instance_index = "NO",
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sld_virtual_jtag_component.sld_instance_index = 0,
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sld_virtual_jtag_component.sld_instance_index = 0,
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sld_virtual_jtag_component.sld_ir_width = 2,
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sld_virtual_jtag_component.sld_ir_width = 2,
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sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
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sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
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sld_virtual_jtag_component.sld_sim_n_scan = 1,
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sld_virtual_jtag_component.sld_sim_n_scan = 1,
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sld_virtual_jtag_component.sld_sim_total_length = 2;
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sld_virtual_jtag_component.sld_sim_total_length = 2;
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endmodule
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endmodule
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