//**************************************************************
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//**************************************************************
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// Module : chipscope_vio_adda_fifo.v
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// Module : chipscope_vio_adda_fifo.v
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// Platform : Ubuntu addr_width.04
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// Platform : Ubuntu addr_width.04
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// Simulator : Modelsim 6.5b
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// Simulator : Modelsim 6.5b
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// Synthesizer : PlanAhead 14.2
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// Synthesizer : PlanAhead 14.2
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// Place and Route : PlanAhead 14.2
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// Place and Route : PlanAhead 14.2
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// Targets device : Zynq-7000
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// Targets device : Zynq-7000
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Organization : www.opencores.org
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// Revision : 2.3
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// Revision : 2.3
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// Date : 2012/11/19
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// Date : 2012/11/19
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// Description : addr/data capture output to debug host
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// Description : addr/data capture output to debug host
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// via Virtual JTAG.
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// via Virtual JTAG.
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//**************************************************************
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//**************************************************************
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module chipscope_vio_adda_fifo(clk,wr_in,data_in,rd_in,icon_ctrl);
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module chipscope_vio_adda_fifo(clk,wr_in,data_in,rd_in,icon_ctrl);
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parameter data_width = 82,
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parameter data_width = 98,
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addr_width = 10,
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addr_width = 10,
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al_full_val = 511;
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al_full_val = 511;
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input clk;
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input clk;
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input wr_in, rd_in;
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input wr_in, rd_in;
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input [data_width-1:0] data_in;
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input [data_width-1:0] data_in;
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inout [35:0] icon_ctrl;
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inout [35:0] icon_ctrl;
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wire [2-1:0] ctrl_vi;
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wire [2-1:0] ctrl_vi;
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wire [addr_width+data_width-1:0] usedw_data_vo;
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wire [addr_width+data_width-1:0] usedw_data_vo;
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reg rst_d1, rst_d2;
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reg rst_d1, rst_d2;
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reg rd_d1 , rd_d2;
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reg rd_d1 , rd_d2;
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always @(posedge clk) begin
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always @(posedge clk) begin
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rst_d1 <= ctrl_vi[1];
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rst_d1 <= ctrl_vi[1];
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rst_d2 <= rst_d1;
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rst_d2 <= rst_d1;
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rd_d1 <= ctrl_vi[0];
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rd_d1 <= ctrl_vi[0];
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rd_d2 <= rd_d1;
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rd_d2 <= rd_d1;
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end
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end
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wire rst_vi = rst_d1 & !rst_d2;
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wire rst_vi = rst_d1 & !rst_d2;
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wire rd_vi = rd_d1 & !rd_d2;
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wire rd_vi = rd_d1 & !rd_d2;
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wire reset = rst_vi;
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wire reset = rst_vi;
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wire [addr_width-1:0] usedw;
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wire [addr_width-1:0] usedw;
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wire [data_width-1:0] data_out;
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wire [data_width-1:0] data_out;
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wire al_full = (usedw==al_full_val)? 1'b1: 1'b0;
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wire al_full = (usedw==al_full_val)? 1'b1: 1'b0;
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wire wr_en = wr_in & !al_full;
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wire wr_en = wr_in & !al_full;
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wire rd_en = rd_in | rd_vi;
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wire rd_en = rd_in | rd_vi;
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assign usedw_data_vo = {usedw, data_out};
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assign usedw_data_vo = {usedw, data_out};
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scfifo jtag_fifo(
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scfifo jtag_fifo(
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.clk(clk),
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.clk(clk),
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.rst(reset),
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.rst(reset),
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.din(data_in),
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.din(data_in),
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.wr_en(wr_en),
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.wr_en(wr_en),
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.rd_en(rd_en),
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.rd_en(rd_en),
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.dout(data_out),
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.dout(data_out),
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.full(),
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.full(),
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.empty(),
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.empty(),
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.data_count(usedw)
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.data_count(usedw)
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);
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);
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chipscope_vio_fifo VIO_inst (
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chipscope_vio_fifo VIO_inst (
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.CONTROL(icon_ctrl), // INOUT BUS [35:0]
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.CONTROL(icon_ctrl), // INOUT BUS [35:0]
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.CLK(clk), // IN
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.CLK(clk), // IN
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.SYNC_OUT(ctrl_vi), // OUT BUS [1:0]
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.SYNC_OUT(ctrl_vi), // OUT BUS [1:0]
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.SYNC_IN(usedw_data_vo) // IN BUS [91:0]
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.SYNC_IN(usedw_data_vo) // IN BUS [107:0]
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);
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);
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endmodule
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endmodule
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