//**************************************************************
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//**************************************************************
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// Module : chipscope_vio_adda_trig.v
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// Module : chipscope_vio_adda_trig.v
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// Platform : Ubuntu pnum_width.04
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// Platform : Ubuntu pnum_width.04
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// Simulator : Modelsim 6.5b
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// Simulator : Modelsim 6.5b
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// Synthesizer : PlanAhead 14.2
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// Synthesizer : PlanAhead 14.2
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// Place and Route : PlanAhead 14.2
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// Place and Route : PlanAhead 14.2
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// Targets device : Zynq-7000
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// Targets device : Zynq-7000
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Organization : www.opencores.org
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// Revision : 2.3
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// Revision : 2.3
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// Date : 2012/11/19
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// Date : 2012/11/19
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// Description : addr/data capture output to debug host
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// Description : addr/data capture output to debug host
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// via Virtual JTAG.
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// via Virtual JTAG.
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//**************************************************************
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//**************************************************************
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module chipscope_vio_adda_trig(trig_out, pnum_out, clk, icon_ctrl);
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module chipscope_vio_adda_trig(trig_out, pnum_out, clk, icon_ctrl);
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parameter trig_width = 56;
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parameter trig_width = 72;
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parameter pnum_width = 10;
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parameter pnum_width = 10;
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output [trig_width-1:0] trig_out;
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output [trig_width-1:0] trig_out;
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output [pnum_width-1:0] pnum_out;
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output [pnum_width-1:0] pnum_out;
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input clk;
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input clk;
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inout [35:0] icon_ctrl;
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inout [35:0] icon_ctrl;
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wire [pnum_width+trig_width-1:0] pnum_trig_vi;
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wire [pnum_width+trig_width-1:0] pnum_trig_vi;
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reg [trig_width-1:0] trig_out;
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reg [trig_width-1:0] trig_out;
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reg [pnum_width-1:0] pnum_out;
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reg [pnum_width-1:0] pnum_out;
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always @(posedge clk) begin
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always @(posedge clk) begin
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pnum_out <= pnum_trig_vi[pnum_width+trig_width-1:trig_width];
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pnum_out <= pnum_trig_vi[pnum_width+trig_width-1:trig_width];
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trig_out <= pnum_trig_vi[ trig_width-1: 0];
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trig_out <= pnum_trig_vi[ trig_width-1: 0];
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end
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end
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chipscope_vio_trig VIO_inst (
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chipscope_vio_trig VIO_inst (
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.CONTROL(icon_ctrl), // INOUT BUS [35:0]
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.CONTROL(icon_ctrl), // INOUT BUS [35:0]
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.CLK(clk), // IN
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.CLK(clk), // IN
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.SYNC_OUT(pnum_trig_vi) // OUT BUS [65:0]
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.SYNC_OUT(pnum_trig_vi) // OUT BUS [81:0]
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);
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);
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endmodule
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endmodule
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