|
|
|
|
xilinx.com
|
xilinx.com
|
project
|
project
|
coregen
|
coregen
|
1.0
|
1.0
|
|
|
|
|
chipscope_icon
|
chipscope_icon
|
|
|
|
|
chipscope_icon
|
chipscope_icon
|
false
|
false
|
3
|
3
|
true
|
true
|
external
|
external
|
false
|
false
|
false
|
false
|
USER1
|
USER1
|
false
|
false
|
|
|
|
|
|
|
|
|
coregen
|
coregen
|
./
|
./
|
./tmp/
|
./tmp/
|
./tmp/_cg/
|
./tmp/_cg/
|
|
|
|
|
xc7z020
|
xc7z020
|
zynq
|
zynq
|
clg400
|
clg400
|
-2
|
-2
|
|
|
|
|
BusFormatAngleBracketNotRipped
|
BusFormatAngleBracketNotRipped
|
Verilog
|
Verilog
|
true
|
true
|
Other
|
Other
|
false
|
false
|
false
|
false
|
false
|
false
|
Ngc
|
Ngc
|
false
|
false
|
|
|
|
|
Behavioral
|
Behavioral
|
Verilog
|
Verilog
|
false
|
false
|
|
|
|
|
2012-07-21+03:11
|
2012-07-21+03:11
|
|
|
|
|
|
|
|
|
|
|
chipscope_vio_fifo
|
chipscope_vio_fifo
|
|
|
|
|
chipscope_vio_fifo
|
chipscope_vio_fifo
|
92
|
108
|
2
|
2
|
false
|
false
|
false
|
false
|
external
|
external
|
false
|
false
|
8
|
8
|
true
|
true
|
8
|
8
|
true
|
true
|
true
|
true
|
8
|
8
|
1
|
1
|
8
|
8
|
1
|
1
|
2
|
2
|
2
|
2
|
0
|
0
|
92
|
108
|
chipscope_vio_fifo
|
chipscope_vio_fifo
|
true
|
true
|
Component_Name=chipscope_vio_fifo;Enable_Synchronous_Input_Port=true;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=false;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=92;Synchronous_Output_Port_Width=2;Asynchronous_Input_Port_Width=8;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false
|
Component_Name=chipscope_vio_fifo;Enable_Synchronous_Input_Port=true;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=false;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=108;Synchronous_Output_Port_Width=2;Asynchronous_Input_Port_Width=8;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false
|
external
|
external
|
0
|
0
|
0
|
0
|
1
|
1
|
|
|
|
|
|
|
|
|
coregen
|
coregen
|
./
|
./
|
./tmp/
|
./tmp/
|
./tmp/_cg/
|
./tmp/_cg/
|
|
|
|
|
xc7z020
|
xc7z020
|
zynq
|
zynq
|
clg400
|
clg400
|
-2
|
-2
|
|
|
|
|
BusFormatAngleBracketNotRipped
|
BusFormatAngleBracketNotRipped
|
Verilog
|
Verilog
|
true
|
true
|
Other
|
Other
|
false
|
false
|
false
|
false
|
false
|
false
|
Ngc
|
Ngc
|
false
|
false
|
|
|
|
|
Structural
|
Structural
|
Verilog
|
Verilog
|
false
|
false
|
|
|
|
|
2012-07-21+03:12
|
2012-10-12+23:08
|
|
|
|
|
|
|
|
|
customization_generator
|
customization_generator
|
|
|
|
|
model_parameter_resolution_generator
|
model_parameter_resolution_generator
|
|
|
|
|
ip_xco_generator
|
ip_xco_generator
|
|
|
./chipscope_vio_fifo.xco
|
./chipscope_vio_fifo.xco
|
xco
|
xco
|
Tue Nov 20 02:34:08 GMT 2012
|
Fri Feb 07 09:32:54 GMT 2014
|
0x8A36FA63
|
0x724012F7
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
|
|
ngc_netlist_generator
|
ngc_netlist_generator
|
|
|
./chipscope_vio_fifo/example_design/chipscope_vio_fifo_bb_lib.v
|
./chipscope_vio_fifo/example_design/chipscope_vio_fifo_bb_lib.v
|
ignore
|
ignore
|
verilogSynthesis
|
verilogSynthesis
|
Tue Nov 20 02:34:09 GMT 2012
|
Fri Feb 07 09:32:54 GMT 2014
|
0x9770D02F
|
0xEC2F0FB0
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.ucf
|
./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.ucf
|
ignore
|
ignore
|
ucf
|
ucf
|
Tue Nov 20 02:34:11 GMT 2012
|
Fri Feb 07 09:32:57 GMT 2014
|
0x1390C322
|
0x1390C322
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.v
|
./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.v
|
ignore
|
ignore
|
verilogSynthesis
|
verilogSynthesis
|
Tue Nov 20 02:34:11 GMT 2012
|
Fri Feb 07 09:32:56 GMT 2014
|
0x3E0AC7FF
|
0x8DB35830
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.xdc
|
./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.xdc
|
ignore
|
ignore
|
xdc
|
xdc
|
Tue Nov 20 02:34:11 GMT 2012
|
Fri Feb 07 09:32:57 GMT 2014
|
0x90E75716
|
0x938BE115
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/implement/chipscope_icon.xco
|
./chipscope_vio_fifo/implement/chipscope_icon.xco
|
ignore
|
ignore
|
xco
|
xco
|
Tue Nov 20 02:34:09 GMT 2012
|
Fri Feb 07 09:32:55 GMT 2014
|
0x1FF80BFB
|
0x1FF80BFB
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/implement/coregen.cgp
|
./chipscope_vio_fifo/implement/coregen.cgp
|
ignore
|
ignore
|
unknown
|
unknown
|
Tue Nov 20 02:34:09 GMT 2012
|
Fri Feb 07 09:32:55 GMT 2014
|
0x940C30DF
|
0x940C30DF
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/implement/example_chipscope_vio_fifo.prj
|
./chipscope_vio_fifo/implement/example_chipscope_vio_fifo.prj
|
ignore
|
ignore
|
unknown
|
unknown
|
Tue Nov 20 02:34:10 GMT 2012
|
Fri Feb 07 09:32:56 GMT 2014
|
0xAE724F77
|
0xAE724F77
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/implement/example_chipscope_vio_fifo.xst
|
./chipscope_vio_fifo/implement/example_chipscope_vio_fifo.xst
|
ignore
|
ignore
|
unknown
|
unknown
|
Tue Nov 20 02:34:13 GMT 2012
|
Fri Feb 07 09:32:58 GMT 2014
|
0xEBBE356D
|
0xEBBE356D
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/implement/ise_implement.bat
|
./chipscope_vio_fifo/implement/ise_implement.bat
|
ignore
|
ignore
|
unknown
|
unknown
|
Tue Nov 20 02:34:10 GMT 2012
|
Fri Feb 07 09:32:55 GMT 2014
|
0xEE86AB45
|
0xEE86AB45
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/implement/ise_implement.sh
|
./chipscope_vio_fifo/implement/ise_implement.sh
|
ignore
|
ignore
|
unknown
|
unknown
|
Tue Nov 20 02:34:13 GMT 2012
|
Fri Feb 07 09:32:58 GMT 2014
|
0x32780610
|
0x32780610
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/implement/pa_ise_implement.tcl
|
./chipscope_vio_fifo/implement/pa_ise_implement.tcl
|
ignore
|
ignore
|
tcl
|
tcl
|
Tue Nov 20 02:34:11 GMT 2012
|
Fri Feb 07 09:32:56 GMT 2014
|
0xC8D9F8F9
|
0xC8D9F8F9
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/implement/rdi_implement.tcl
|
./chipscope_vio_fifo/implement/rdi_implement.tcl
|
ignore
|
ignore
|
tcl
|
tcl
|
Tue Nov 20 02:34:12 GMT 2012
|
Fri Feb 07 09:32:57 GMT 2014
|
0xBD351EB6
|
0xBD351EB6
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/implement/v_rdi_implement.tcl
|
./chipscope_vio_fifo/implement/v_rdi_implement.tcl
|
ignore
|
ignore
|
tcl
|
tcl
|
Tue Nov 20 02:34:12 GMT 2012
|
Fri Feb 07 09:32:58 GMT 2014
|
0x74FFDD3B
|
0x74FFDD3B
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo/read_me.txt
|
./chipscope_vio_fifo/read_me.txt
|
ignore
|
ignore
|
txt
|
txt
|
Tue Nov 20 02:34:12 GMT 2012
|
Fri Feb 07 09:32:58 GMT 2014
|
0x4A2AE78B
|
0xCE4AA0B8
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo.cdc
|
./chipscope_vio_fifo.cdc
|
unknown
|
unknown
|
Tue Nov 20 02:35:09 GMT 2012
|
Fri Feb 07 09:33:59 GMT 2014
|
0xB3886A39
|
0x4CA21057
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo.constraints/chipscope_vio_fifo.ucf
|
./chipscope_vio_fifo.constraints/chipscope_vio_fifo.ucf
|
ucf
|
ucf
|
Tue Nov 20 02:35:09 GMT 2012
|
Fri Feb 07 09:33:59 GMT 2014
|
0x46D4F328
|
0x46D4F328
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo.constraints/chipscope_vio_fifo.xdc
|
./chipscope_vio_fifo.constraints/chipscope_vio_fifo.xdc
|
xdc
|
xdc
|
Tue Nov 20 02:35:09 GMT 2012
|
Fri Feb 07 09:33:59 GMT 2014
|
0xC2D11607
|
0xC2D11607
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo.ngc
|
./chipscope_vio_fifo.ngc
|
ngc
|
ngc
|
Tue Nov 20 02:35:08 GMT 2012
|
Fri Feb 07 09:33:57 GMT 2014
|
0xB712EB26
|
0xD2121D98
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo.ucf
|
./chipscope_vio_fifo.ucf
|
ignore
|
ignore
|
ucf
|
ucf
|
Tue Nov 20 02:35:09 GMT 2012
|
Fri Feb 07 09:33:59 GMT 2014
|
0x46D4F328
|
0x46D4F328
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo.v
|
./chipscope_vio_fifo.v
|
verilog
|
verilog
|
verilogSynthesis
|
verilogSynthesis
|
Tue Nov 20 02:35:09 GMT 2012
|
Fri Feb 07 09:33:59 GMT 2014
|
0x84C0DD82
|
0x81491EFF
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo.veo
|
./chipscope_vio_fifo.veo
|
veo
|
veo
|
Tue Nov 20 02:35:09 GMT 2012
|
Fri Feb 07 09:33:59 GMT 2014
|
0xEA70F2E8
|
0x9DE1BF59
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo.xdc
|
./chipscope_vio_fifo.xdc
|
ignore
|
ignore
|
xdc
|
xdc
|
Tue Nov 20 02:35:09 GMT 2012
|
Fri Feb 07 09:33:59 GMT 2014
|
0xC2D11607
|
0xC2D11607
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo_xmdf.tcl
|
./chipscope_vio_fifo_xmdf.tcl
|
tcl
|
tcl
|
Tue Nov 20 02:34:12 GMT 2012
|
Fri Feb 07 09:32:58 GMT 2014
|
0x136E503B
|
0x136E503B
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
|
|
instantiation_template_generator
|
instantiation_template_generator
|
|
|
|
|
asy_generator
|
asy_generator
|
|
|
./chipscope_vio_fifo.asy
|
./chipscope_vio_fifo.asy
|
asy
|
asy
|
Tue Nov 20 02:35:10 GMT 2012
|
Fri Feb 07 09:33:59 GMT 2014
|
0xEE4A2520
|
0x42C0F37B
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
|
|
xmdf_generator
|
xmdf_generator
|
|
|
|
|
ise_generator
|
ise_generator
|
|
|
./chipscope_vio_fifo.gise
|
./chipscope_vio_fifo.gise
|
ignore
|
ignore
|
gise
|
gise
|
Tue Nov 20 02:35:14 GMT 2012
|
Fri Feb 07 09:34:07 GMT 2014
|
0xE46738AE
|
0xE46738AE
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
./chipscope_vio_fifo.xise
|
./chipscope_vio_fifo.xise
|
ignore
|
ignore
|
xise
|
xise
|
Tue Nov 20 02:35:14 GMT 2012
|
Fri Feb 07 09:34:07 GMT 2014
|
0x78819C93
|
0x0BED329B
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
|
|
deliver_readme_generator
|
deliver_readme_generator
|
|
|
./chipscope_vio_fifo_readme.txt
|
./chipscope_vio_fifo_readme.txt
|
ignore
|
ignore
|
txtReadme
|
txtReadme
|
txt
|
txt
|
Tue Nov 20 02:35:14 GMT 2012
|
Fri Feb 07 09:34:07 GMT 2014
|
0x8A5D60C8
|
0xEA5F9500
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
|
|
flist_generator
|
flist_generator
|
|
|
./chipscope_vio_fifo_flist.txt
|
./chipscope_vio_fifo_flist.txt
|
ignore
|
ignore
|
txtFlist
|
txtFlist
|
txt
|
txt
|
Tue Nov 20 02:35:14 GMT 2012
|
Fri Feb 07 09:34:07 GMT 2014
|
0x2E57030C
|
0x2E57030C
|
generationID_4013899584
|
generationID_1879581046
|
|
|
|
|
|
|
view_readme_generator
|
view_readme_generator
|
|
|
|
|
|
|
|
|
|
|
chipscope_vio_mask
|
chipscope_vio_mask
|
|
|
|
|
chipscope_vio_mask
|
chipscope_vio_mask
|
8
|
8
|
40
|
40
|
false
|
false
|
false
|
false
|
external
|
external
|
false
|
false
|
8
|
8
|
true
|
true
|
8
|
8
|
false
|
false
|
true
|
true
|
8
|
|
1
|
|
8
|
|
0
|
|
2
|
|
40
|
|
0
|
|
8
|
|
chipscope_vio_mask
|
|
true
|
|
Component_Name=chipscope_vio_mask;Enable_Synchronous_Input_Port=false;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=false;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=8;Synchronous_Output_Port_Width=40;Asynchronous_Input_Port_Width=8;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false
|
|
external
|
|
0
|
|
0
|
|
1
|
|
|
|
|
|
|
|
|
|
coregen
|
coregen
|
./
|
./
|
./tmp/
|
./tmp/
|
./tmp/_cg/
|
./tmp/_cg/
|
|
|
|
|
xc7z020
|
xc7z020
|
zynq
|
zynq
|
clg400
|
clg400
|
-2
|
-2
|
|
|
|
|
BusFormatAngleBracketNotRipped
|
BusFormatAngleBracketNotRipped
|
Verilog
|
Verilog
|
true
|
true
|
Other
|
Other
|
false
|
false
|
false
|
false
|
false
|
false
|
Ngc
|
Ngc
|
false
|
false
|
|
|
|
|
Structural
|
Structural
|
Verilog
|
Verilog
|
false
|
false
|
|
|
|
|
2012-07-21+03:12
|
2012-07-21+03:12
|
|
|
|
|
|
|
|
|
customization_generator
|
|
|
|
|
|
model_parameter_resolution_generator
|
|
|
|
|
|
ip_xco_generator
|
|
|
|
./chipscope_vio_mask.xco
|
|
xco
|
|
Tue Nov 20 02:35:57 GMT 2012
|
|
0xE543A821
|
|
generationID_1879581046
|
|
|
|
|
|
|
|
ngc_netlist_generator
|
|
|
|
./chipscope_vio_mask/example_design/chipscope_vio_mask_bb_lib.v
|
|
ignore
|
|
verilogSynthesis
|
|
Tue Nov 20 02:35:57 GMT 2012
|
|
0x8C39E98A
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/example_design/example_chipscope_vio_mask.ucf
|
|
ignore
|
|
ucf
|
|
Tue Nov 20 02:36:00 GMT 2012
|
|
0x8A99C5D7
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/example_design/example_chipscope_vio_mask.v
|
|
ignore
|
|
verilogSynthesis
|
|
Tue Nov 20 02:35:59 GMT 2012
|
|
0x75E2D857
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/example_design/example_chipscope_vio_mask.xdc
|
|
ignore
|
|
xdc
|
|
Tue Nov 20 02:36:00 GMT 2012
|
|
0xED983B09
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/implement/chipscope_icon.xco
|
|
ignore
|
|
xco
|
|
Tue Nov 20 02:35:58 GMT 2012
|
|
0x1FF80BFB
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/implement/coregen.cgp
|
|
ignore
|
|
unknown
|
|
Tue Nov 20 02:35:58 GMT 2012
|
|
0x940C30DF
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/implement/example_chipscope_vio_mask.prj
|
|
ignore
|
|
unknown
|
|
Tue Nov 20 02:35:59 GMT 2012
|
|
0xDD5C1574
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/implement/example_chipscope_vio_mask.xst
|
|
ignore
|
|
unknown
|
|
Tue Nov 20 02:36:01 GMT 2012
|
|
0x95BB138E
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/implement/ise_implement.bat
|
|
ignore
|
|
unknown
|
|
Tue Nov 20 02:35:58 GMT 2012
|
|
0xEF02D4FF
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/implement/ise_implement.sh
|
|
ignore
|
|
unknown
|
|
Tue Nov 20 02:36:01 GMT 2012
|
|
0x9A745C3F
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/implement/pa_ise_implement.tcl
|
|
ignore
|
|
tcl
|
|
Tue Nov 20 02:35:59 GMT 2012
|
|
0xF047984E
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/implement/rdi_implement.tcl
|
|
ignore
|
|
tcl
|
|
Tue Nov 20 02:36:00 GMT 2012
|
|
0x5B9127B8
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/implement/v_rdi_implement.tcl
|
|
ignore
|
|
tcl
|
|
Tue Nov 20 02:36:00 GMT 2012
|
|
0x94CF2579
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask/read_me.txt
|
|
ignore
|
|
txt
|
|
Tue Nov 20 02:36:01 GMT 2012
|
|
0x4A2AE78B
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask.cdc
|
|
unknown
|
|
Tue Nov 20 02:36:39 GMT 2012
|
|
0xA96F5278
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask.constraints/chipscope_vio_mask.ucf
|
|
ucf
|
|
Tue Nov 20 02:36:39 GMT 2012
|
|
0x46D4F328
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask.constraints/chipscope_vio_mask.xdc
|
|
xdc
|
|
Tue Nov 20 02:36:39 GMT 2012
|
|
0xC2D11607
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask.ngc
|
|
ngc
|
|
Tue Nov 20 02:36:38 GMT 2012
|
|
0xE1997330
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask.ucf
|
|
ignore
|
|
ucf
|
|
Tue Nov 20 02:36:39 GMT 2012
|
|
0x46D4F328
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask.v
|
|
verilog
|
|
verilogSynthesis
|
|
Tue Nov 20 02:36:39 GMT 2012
|
|
0x78FBC74D
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask.veo
|
|
veo
|
|
Tue Nov 20 02:36:39 GMT 2012
|
|
0xAF798824
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask.xdc
|
|
ignore
|
|
xdc
|
|
Tue Nov 20 02:36:39 GMT 2012
|
|
0xC2D11607
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask_xmdf.tcl
|
|
tcl
|
|
Tue Nov 20 02:36:01 GMT 2012
|
|
0xBADC42BD
|
|
generationID_1879581046
|
|
|
|
|
|
|
|
instantiation_template_generator
|
|
|
|
|
|
asy_generator
|
|
|
|
./chipscope_vio_mask.asy
|
|
asy
|
|
Tue Nov 20 02:36:40 GMT 2012
|
|
0xB7DFDEC6
|
|
generationID_1879581046
|
|
|
|
|
|
|
|
xmdf_generator
|
|
|
|
|
|
ise_generator
|
|
|
|
./chipscope_vio_mask.gise
|
|
ignore
|
|
gise
|
|
Tue Nov 20 02:36:44 GMT 2012
|
|
0x81874387
|
|
generationID_1879581046
|
|
|
|
|
|
./chipscope_vio_mask.xise
|
|
ignore
|
|
xise
|
|
Tue Nov 20 02:36:44 GMT 2012
|
|
0xD0AB24F1
|
|
generationID_1879581046
|
|
|
|
|
|
|
|
deliver_readme_generator
|
|
|
|
./chipscope_vio_mask_readme.txt
|
|
ignore
|
|
txtReadme
|
|
txt
|
|
Tue Nov 20 02:36:44 GMT 2012
|
|
0x736C765D
|
|
generationID_1879581046
|
|
|
|
|
|
|
|
flist_generator
|
|
|
|
./chipscope_vio_mask_flist.txt
|
|
ignore
|
|
txtFlist
|
|
txt
|
|
Tue Nov 20 02:36:44 GMT 2012
|
|
0x1CC0385A
|
|
generationID_1879581046
|
|
|
|
|
|
|
|
view_readme_generator
|
|
|
|
|
|
|
|
|
|
|
|
chipscope_vio_trig
|
chipscope_vio_trig
|
|
|
|
|
chipscope_vio_trig
|
chipscope_vio_trig
|
8
|
8
|
66
|
82
|
false
|
false
|
false
|
false
|
external
|
external
|
false
|
false
|
8
|
8
|
true
|
true
|
8
|
8
|
false
|
false
|
true
|
true
|
8
|
|
1
|
|
8
|
|
0
|
|
2
|
|
66
|
|
0
|
|
8
|
|
chipscope_vio_trig
|
|
true
|
|
Component_Name=chipscope_vio_trig;Enable_Synchronous_Input_Port=false;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=false;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=8;Synchronous_Output_Port_Width=66;Asynchronous_Input_Port_Width=8;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false
|
|
external
|
|
0
|
|
0
|
|
1
|
|
|
|
|
|
|
|
|
|
coregen
|
coregen
|
./
|
./
|
./tmp/
|
./tmp/
|
./tmp/_cg/
|
./tmp/_cg/
|
|
|
|
|
xc7z020
|
xc7z020
|
zynq
|
zynq
|
clg400
|
clg400
|
-2
|
-2
|
|
|
|
|
BusFormatAngleBracketNotRipped
|
BusFormatAngleBracketNotRipped
|
Verilog
|
Verilog
|
true
|
true
|
Other
|
Other
|
false
|
false
|
false
|
false
|
false
|
false
|
Ngc
|
Ngc
|
false
|
false
|
|
|
|
|
Structural
|
Structural
|
Verilog
|
Verilog
|
false
|
false
|
|
|
|
|
2012-07-21+03:12
|
2012-10-12+23:08
|
|
|
|
|
|
|
|
|
customization_generator
|
|
|
|
|
|
model_parameter_resolution_generator
|
|
|
|
|
|
ip_xco_generator
|
|
|
|
./chipscope_vio_trig.xco
|
|
xco
|
|
Tue Nov 20 02:37:14 GMT 2012
|
|
0x1C211B73
|
|
generationID_3673615094
|
|
|
|
|
|
|
|
ngc_netlist_generator
|
|
|
|
./chipscope_vio_trig/example_design/chipscope_vio_trig_bb_lib.v
|
|
ignore
|
|
verilogSynthesis
|
|
Tue Nov 20 02:37:15 GMT 2012
|
|
0x4FF83256
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/example_design/example_chipscope_vio_trig.ucf
|
|
ignore
|
|
ucf
|
|
Tue Nov 20 02:37:17 GMT 2012
|
|
0xB859E54F
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/example_design/example_chipscope_vio_trig.v
|
|
ignore
|
|
verilogSynthesis
|
|
Tue Nov 20 02:37:17 GMT 2012
|
|
0x604E80B9
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/example_design/example_chipscope_vio_trig.xdc
|
|
ignore
|
|
xdc
|
|
Tue Nov 20 02:37:17 GMT 2012
|
|
0x2338DEFF
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/implement/chipscope_icon.xco
|
|
ignore
|
|
xco
|
|
Tue Nov 20 02:37:15 GMT 2012
|
|
0x1FF80BFB
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/implement/coregen.cgp
|
|
ignore
|
|
unknown
|
|
Tue Nov 20 02:37:15 GMT 2012
|
|
0x940C30DF
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/implement/example_chipscope_vio_trig.prj
|
|
ignore
|
|
unknown
|
|
Tue Nov 20 02:37:16 GMT 2012
|
|
0x34375C50
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/implement/example_chipscope_vio_trig.xst
|
|
ignore
|
|
unknown
|
|
Tue Nov 20 02:37:18 GMT 2012
|
|
0x8A9B51FF
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/implement/ise_implement.bat
|
|
ignore
|
|
unknown
|
|
Tue Nov 20 02:37:15 GMT 2012
|
|
0xD215B1A8
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/implement/ise_implement.sh
|
|
ignore
|
|
unknown
|
|
Tue Nov 20 02:37:18 GMT 2012
|
|
0x2A4B1B2C
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/implement/pa_ise_implement.tcl
|
|
ignore
|
|
tcl
|
|
Tue Nov 20 02:37:16 GMT 2012
|
|
0x2C7947C8
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/implement/rdi_implement.tcl
|
|
ignore
|
|
tcl
|
|
Tue Nov 20 02:37:17 GMT 2012
|
|
0x3BC95413
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/implement/v_rdi_implement.tcl
|
|
ignore
|
|
tcl
|
|
Tue Nov 20 02:37:18 GMT 2012
|
|
0x7F500418
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig/read_me.txt
|
|
ignore
|
|
txt
|
|
Tue Nov 20 02:37:18 GMT 2012
|
|
0x4A2AE78B
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig.cdc
|
|
unknown
|
|
Tue Nov 20 02:37:58 GMT 2012
|
|
0x97DAF80B
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig.constraints/chipscope_vio_trig.ucf
|
|
ucf
|
|
Tue Nov 20 02:37:58 GMT 2012
|
|
0x46D4F328
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig.constraints/chipscope_vio_trig.xdc
|
|
xdc
|
|
Tue Nov 20 02:37:58 GMT 2012
|
|
0xC2D11607
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig.ngc
|
|
ngc
|
|
Tue Nov 20 02:37:56 GMT 2012
|
|
0xE667CCD8
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig.ucf
|
|
ignore
|
|
ucf
|
|
Tue Nov 20 02:37:58 GMT 2012
|
|
0x46D4F328
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig.v
|
|
verilog
|
|
verilogSynthesis
|
|
Tue Nov 20 02:37:58 GMT 2012
|
|
0x22E2DC33
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig.veo
|
|
veo
|
|
Tue Nov 20 02:37:58 GMT 2012
|
|
0x4BA52A8E
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig.xdc
|
|
ignore
|
|
xdc
|
|
Tue Nov 20 02:37:58 GMT 2012
|
|
0xC2D11607
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig_xmdf.tcl
|
|
tcl
|
|
Tue Nov 20 02:37:18 GMT 2012
|
|
0x0BB32865
|
|
generationID_3673615094
|
|
|
|
|
|
|
|
instantiation_template_generator
|
|
|
|
|
|
asy_generator
|
|
|
|
./chipscope_vio_trig.asy
|
|
asy
|
|
Tue Nov 20 02:37:58 GMT 2012
|
|
0x7C5E1854
|
|
generationID_3673615094
|
|
|
|
|
|
|
|
xmdf_generator
|
|
|
|
|
|
ise_generator
|
|
|
|
./chipscope_vio_trig.gise
|
|
ignore
|
|
gise
|
|
Tue Nov 20 02:38:02 GMT 2012
|
|
0xD388EB56
|
|
generationID_3673615094
|
|
|
|
|
|
./chipscope_vio_trig.xise
|
|
ignore
|
|
xise
|
|
Tue Nov 20 02:38:02 GMT 2012
|
|
0x20B90E56
|
|
generationID_3673615094
|
|
|
|
|
|
|
|
deliver_readme_generator
|
|
|
|
./chipscope_vio_trig_readme.txt
|
|
ignore
|
|
txtReadme
|
|
txt
|
|
Tue Nov 20 02:38:02 GMT 2012
|
|
0x7BAD3427
|
|
generationID_3673615094
|
|
|
|
|
|
|
|
flist_generator
|
|
|
|
./chipscope_vio_trig_flist.txt
|
|
ignore
|
|
txtFlist
|
|
txt
|
|
Tue Nov 20 02:38:02 GMT 2012
|
|
0x4B4A8590
|
|
generationID_3673615094
|
|
|
|
|
|
|
|
view_readme_generator
|
|
|
|
|
|
|
|
|
|
|
|
scfifo
|
scfifo
|
|
|
|
|
scfifo
|
scfifo
|
Common_Clock_Block_RAM
|
Common_Clock_Block_RAM
|
2
|
2
|
2
|
2
|
Native
|
Native
|
Standard_FIFO
|
Standard_FIFO
|
82
|
98
|
1024
|
1024
|
82
|
98
|
1024
|
1024
|
false
|
false
|
false
|
false
|
true
|
true
|
true
|
true
|
Asynchronous_Reset
|
Asynchronous_Reset
|
1
|
1
|
true
|
true
|
0
|
0
|
false
|
false
|
false
|
false
|
false
|
false
|
Active_High
|
Active_High
|
false
|
false
|
Active_High
|
Active_High
|
false
|
false
|
Active_High
|
Active_High
|
false
|
false
|
Active_High
|
Active_High
|
false
|
false
|
false
|
false
|
false
|
false
|
true
|
true
|
10
|
10
|
false
|
false
|
10
|
10
|
false
|
false
|
10
|
10
|
false
|
false
|
1
|
1
|
1
|
1
|
No_Programmable_Full_Threshold
|
No_Programmable_Full_Threshold
|
1022
|
1022
|
1021
|
1021
|
No_Programmable_Empty_Threshold
|
No_Programmable_Empty_Threshold
|
2
|
2
|
3
|
3
|
AXI4_Stream
|
AXI4_Stream
|
Common_Clock
|
Common_Clock
|
false
|
false
|
Slave_Interface_Clock_Enable
|
Slave_Interface_Clock_Enable
|
false
|
false
|
false
|
false
|
4
|
4
|
32
|
32
|
64
|
64
|
false
|
false
|
1
|
1
|
false
|
false
|
1
|
1
|
false
|
false
|
1
|
1
|
false
|
false
|
1
|
1
|
false
|
false
|
1
|
1
|
false
|
false
|
64
|
64
|
false
|
false
|
8
|
8
|
false
|
false
|
4
|
4
|
false
|
false
|
4
|
4
|
true
|
true
|
false
|
false
|
false
|
false
|
4
|
4
|
false
|
false
|
4
|
4
|
FIFO
|
FIFO
|
Common_Clock_Block_RAM
|
Common_Clock_Block_RAM
|
Data_FIFO
|
Data_FIFO
|
false
|
false
|
false
|
false
|
false
|
false
|
16
|
16
|
false
|
false
|
No_Programmable_Full_Threshold
|
No_Programmable_Full_Threshold
|
1023
|
1023
|
No_Programmable_Empty_Threshold
|
No_Programmable_Empty_Threshold
|
1022
|
1022
|
FIFO
|
FIFO
|
Common_Clock_Block_RAM
|
Common_Clock_Block_RAM
|
Data_FIFO
|
Data_FIFO
|
false
|
false
|
false
|
false
|
false
|
false
|
1024
|
1024
|
false
|
false
|
No_Programmable_Full_Threshold
|
No_Programmable_Full_Threshold
|
1023
|
1023
|
No_Programmable_Empty_Threshold
|
No_Programmable_Empty_Threshold
|
1022
|
1022
|
FIFO
|
FIFO
|
Common_Clock_Block_RAM
|
Common_Clock_Block_RAM
|
Data_FIFO
|
Data_FIFO
|
false
|
false
|
false
|
false
|
false
|
false
|
16
|
16
|
false
|
false
|
No_Programmable_Full_Threshold
|
No_Programmable_Full_Threshold
|
1023
|
1023
|
No_Programmable_Empty_Threshold
|
No_Programmable_Empty_Threshold
|
1022
|
1022
|
FIFO
|
FIFO
|
Common_Clock_Block_RAM
|
Common_Clock_Block_RAM
|
Data_FIFO
|
Data_FIFO
|
false
|
false
|
false
|
false
|
false
|
false
|
16
|
16
|
false
|
false
|
No_Programmable_Full_Threshold
|
No_Programmable_Full_Threshold
|
1023
|
1023
|
No_Programmable_Empty_Threshold
|
No_Programmable_Empty_Threshold
|
1022
|
1022
|
FIFO
|
FIFO
|
Common_Clock_Block_RAM
|
Common_Clock_Block_RAM
|
Data_FIFO
|
Data_FIFO
|
false
|
false
|
false
|
false
|
false
|
false
|
1024
|
1024
|
false
|
false
|
No_Programmable_Full_Threshold
|
No_Programmable_Full_Threshold
|
1023
|
1023
|
No_Programmable_Empty_Threshold
|
No_Programmable_Empty_Threshold
|
1022
|
1022
|
FIFO
|
FIFO
|
Common_Clock_Block_RAM
|
Common_Clock_Block_RAM
|
Data_FIFO
|
Data_FIFO
|
false
|
false
|
false
|
false
|
false
|
false
|
1024
|
1024
|
false
|
false
|
No_Programmable_Full_Threshold
|
No_Programmable_Full_Threshold
|
1023
|
1023
|
No_Programmable_Empty_Threshold
|
No_Programmable_Empty_Threshold
|
1022
|
1022
|
Fully_Registered
|
Fully_Registered
|
Fully_Registered
|
Fully_Registered
|
Fully_Registered
|
Fully_Registered
|
Fully_Registered
|
Fully_Registered
|
Fully_Registered
|
Fully_Registered
|
Fully_Registered
|
Fully_Registered
|
false
|
false
|
Active_High
|
Active_High
|
false
|
false
|
Active_High
|
Active_High
|
false
|
false
|
false
|
false
|
false
|
false
|
false
|
false
|
false
|
false
|
|
|
|
|
|
|
|
|
coregen
|
coregen
|
./
|
./
|
./tmp/
|
./tmp/
|
./tmp/_cg/
|
./tmp/_cg/
|
|
|
|
|
xc7z020
|
xc7z020
|
zynq
|
zynq
|
clg400
|
clg400
|
-2
|
-2
|
|
|
|
|
BusFormatAngleBracketNotRipped
|
BusFormatAngleBracketNotRipped
|
Verilog
|
Verilog
|
true
|
true
|
Other
|
Other
|
false
|
false
|
false
|
false
|
false
|
false
|
Ngc
|
Ngc
|
false
|
false
|
|
|
|
|
Behavioral
|
Behavioral
|
Verilog
|
Verilog
|
false
|
false
|
|
|
|
|
2012-06-23+13:35
|
2012-06-23+13:35
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
coregen
|
coregen
|
./
|
./
|
./tmp/
|
./tmp/
|
./tmp/_cg/
|
./tmp/_cg/
|
|
|
|
|
xc7z020
|
xc7z020
|
zynq
|
zynq
|
clg400
|
clg400
|
-2
|
-2
|
|
|
|
|
BusFormatAngleBracketNotRipped
|
BusFormatAngleBracketNotRipped
|
Verilog
|
Verilog
|
true
|
true
|
Other
|
Other
|
false
|
false
|
false
|
false
|
false
|
false
|
Ngc
|
Ngc
|
false
|
false
|
|
|
|
|
Behavioral
|
Behavioral
|
Verilog
|
Verilog
|
false
|
false
|
|
|
|
|
|
|
|
|
|
|
|
|