URL
https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
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| Rev 18 |
Rev 20 |
# Date: Mon Nov 19 08:26:59 2012
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# Date: Mon Nov 19 08:26:59 2012
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SET addpads = false
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SET addpads = false
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SET asysymbol = true
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET createndf = false
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SET designentry = Verilog
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SET designentry = Verilog
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SET device = xc7z020
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SET device = xc7z020
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SET devicefamily = zynq
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SET devicefamily = zynq
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SET flowvendor = Other
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SET flowvendor = Other
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SET formalverification = false
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SET formalverification = false
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SET foundationsym = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET implementationfiletype = Ngc
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SET package = clg400
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SET package = clg400
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SET removerpms = false
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET speedgrade = -2
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SET verilogsim = true
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SET verilogsim = true
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SET vhdlsim = false
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SET vhdlsim = false
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SET workingdirectory = .\tmp\
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SET workingdirectory = .\tmp\
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# CRC: 7162d0b
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# CRC: 7162d0b
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