//**************************************************************
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//**************************************************************
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// Module : bustap_jtag.v
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// Module : bustap_jtag.v
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// Platform : Ubuntu 10.04
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// Platform : Ubuntu 10.04
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// Simulator : Modelsim 6.5b
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// Simulator : Modelsim 6.5b
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// Synthesizer : PlanAhead 14.2
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// Synthesizer : PlanAhead 14.2
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// Place and Route : PlanAhead 14.2
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// Place and Route : PlanAhead 14.2
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// Targets device : Zynq 7000
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// Targets device : Zynq 7000
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Organization : www.opencores.org
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// Revision : 2.3
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// Revision : 2.3
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// Date : 2012/11/19
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// Date : 2012/11/19
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// Description : axi interface to pipelined access
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// Description : axi interface to pipelined access
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// interface converter.
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// interface converter.
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// @Note: AXI-Lite is supported.
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// @Note: AXI-Lite is supported.
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//**************************************************************
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//**************************************************************
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module bustap_jtag (
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module bustap_jtag (
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// Global Signals
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// Global Signals
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ACLK,
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ACLK,
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ARESETN,
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ARESETN,
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// Write Address Channel
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// Write Address Channel
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AWADDR,
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AWADDR,
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AWPROT,
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AWPROT,
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AWVALID,
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AWVALID,
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AWREADY,
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AWREADY,
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// Write Channel
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// Write Channel
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WDATA,
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WDATA,
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WSTRB,
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WSTRB,
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WVALID,
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WVALID,
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WREADY,
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WREADY,
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// Write Response Channel
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// Write Response Channel
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BRESP,
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BRESP,
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BVALID,
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BVALID,
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BREADY,
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BREADY,
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// Read Address Channel
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// Read Address Channel
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ARADDR,
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ARADDR,
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ARPROT,
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ARPROT,
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ARVALID,
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ARVALID,
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ARREADY,
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ARREADY,
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// Read Channel
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// Read Channel
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RDATA,
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RDATA,
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RRESP,
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RRESP,
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RVALID,
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RVALID,
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RREADY,
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RREADY,
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CHIPSCOPE_ICON_CONTROL0,
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CHIPSCOPE_ICON_CONTROL0,
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CHIPSCOPE_ICON_CONTROL1,
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CHIPSCOPE_ICON_CONTROL1,
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CHIPSCOPE_ICON_CONTROL2
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CHIPSCOPE_ICON_CONTROL2
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);
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);
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// Set C_DATA_WIDTH to the data-bus width required
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// Set C_DATA_WIDTH to the data-bus width required
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parameter C_DATA_WIDTH = 32; // data bus width, default = 32-bit
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parameter C_DATA_WIDTH = 32; // data bus width, default = 32-bit
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// Set C_ADDR_WIDTH to the address-bus width required
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// Set C_ADDR_WIDTH to the address-bus width required
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parameter C_ADDR_WIDTH = 32; // address bus width, default = 32-bit
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parameter C_ADDR_WIDTH = 32; // address bus width, default = 32-bit
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localparam DATA_MAX = C_DATA_WIDTH-1; // data max index
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localparam DATA_MAX = C_DATA_WIDTH-1; // data max index
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localparam ADDR_MAX = C_ADDR_WIDTH-1; // address max index
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localparam ADDR_MAX = C_ADDR_WIDTH-1; // address max index
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localparam STRB_WIDTH = C_DATA_WIDTH/8; // WSTRB width
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localparam STRB_WIDTH = C_DATA_WIDTH/8; // WSTRB width
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localparam STRB_MAX = STRB_WIDTH-1; // WSTRB max index
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localparam STRB_MAX = STRB_WIDTH-1; // WSTRB max index
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// - Global Signals
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// - Global Signals
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input ACLK; // AXI Clock
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input ACLK; // AXI Clock
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input ARESETN; // AXI Reset
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input ARESETN; // AXI Reset
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// - Write Address Channel
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// - Write Address Channel
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input [ADDR_MAX:0] AWADDR; // M -> S
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input [ADDR_MAX:0] AWADDR; // M -> S
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input [2:0] AWPROT; // M -> S
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input [2:0] AWPROT; // M -> S
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input AWVALID; // M -> S
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input AWVALID; // M -> S
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input AWREADY; // S -> M
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input AWREADY; // S -> M
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// - Write Data Channel
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// - Write Data Channel
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input WVALID; // M -> S
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input WVALID; // M -> S
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input WREADY; // S -> M
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input WREADY; // S -> M
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input [DATA_MAX:0] WDATA; // M -> S
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input [DATA_MAX:0] WDATA; // M -> S
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input [STRB_MAX:0] WSTRB; // M -> S
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input [STRB_MAX:0] WSTRB; // M -> S
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// - Write Response Channel
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// - Write Response Channel
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input [1:0] BRESP; // S -> M
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input [1:0] BRESP; // S -> M
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input BVALID; // S -> M
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input BVALID; // S -> M
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input BREADY; // M -> S
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input BREADY; // M -> S
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// - Read Address Channel
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// - Read Address Channel
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input [ADDR_MAX:0] ARADDR; // M -> S
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input [ADDR_MAX:0] ARADDR; // M -> S
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input [2:0] ARPROT; // M -> S
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input [2:0] ARPROT; // M -> S
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input ARVALID; // M -> S
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input ARVALID; // M -> S
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input ARREADY; // S -> M
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input ARREADY; // S -> M
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// - Read Data Channel
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// - Read Data Channel
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input [DATA_MAX:0] RDATA; // S -> M
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input [DATA_MAX:0] RDATA; // S -> M
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input [1:0] RRESP; // S -> M
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input [1:0] RRESP; // S -> M
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input RVALID; // S -> M
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input RVALID; // S -> M
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input RREADY; // M -> S
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input RREADY; // M -> S
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input [35:0] CHIPSCOPE_ICON_CONTROL0, CHIPSCOPE_ICON_CONTROL1, CHIPSCOPE_ICON_CONTROL2;
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input [35:0] CHIPSCOPE_ICON_CONTROL0, CHIPSCOPE_ICON_CONTROL1, CHIPSCOPE_ICON_CONTROL2;
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// latch address and data
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// latch address and data
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reg [ADDR_MAX:0] addr_latch;
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reg [ADDR_MAX:0] addr_latch;
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always @(posedge ACLK) begin
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always @(posedge ACLK) begin
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if (AWVALID && AWREADY)
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if (AWVALID && AWREADY)
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addr_latch <= AWADDR;
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addr_latch <= AWADDR;
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else if (ARVALID && ARREADY)
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else if (ARVALID && ARREADY)
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addr_latch <= ARADDR;
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addr_latch <= ARADDR;
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else
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else
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addr_latch <= addr_latch;
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addr_latch <= addr_latch;
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end
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end
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reg [DATA_MAX:0] data_latch;
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reg [DATA_MAX:0] data_latch;
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always @(posedge ACLK) begin
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always @(posedge ACLK) begin
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if (WVALID && WREADY)
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if (WVALID && WREADY)
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data_latch <= WDATA;
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data_latch <= WDATA;
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else if (RVALID && RREADY)
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else if (RVALID && RREADY)
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data_latch <= RDATA;
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data_latch <= RDATA;
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else
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else
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data_latch <= data_latch;
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data_latch <= data_latch;
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end
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end
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// generate wr/rd pulse
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// generate wr/rd pulse
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reg wr_pulse;
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reg wr_pulse;
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always @(posedge ACLK or negedge ARESETN) begin
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always @(posedge ACLK or negedge ARESETN) begin
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if (!ARESETN)
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if (!ARESETN)
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wr_pulse <= 1'b0;
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wr_pulse <= 1'b0;
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else if (WVALID && WREADY)
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else if (WVALID && WREADY)
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wr_pulse <= 1'b1;
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wr_pulse <= 1'b1;
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else
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else
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wr_pulse <= 1'b0;
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wr_pulse <= 1'b0;
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end
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end
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reg rd_pulse;
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reg rd_pulse;
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always @(posedge ACLK or negedge ARESETN) begin
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always @(posedge ACLK or negedge ARESETN) begin
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if (!ARESETN)
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if (!ARESETN)
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rd_pulse <= 1'b0;
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rd_pulse <= 1'b0;
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else if (RVALID && RREADY)
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else if (RVALID && RREADY)
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rd_pulse <= 1'b1;
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rd_pulse <= 1'b1;
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else
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else
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rd_pulse <= 1'b0;
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rd_pulse <= 1'b0;
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end
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end
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// map to pipelined access interface
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// map to pipelined access interface
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wire clk = ACLK;
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wire clk = ACLK;
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wire wr_en = wr_pulse;
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wire wr_en = wr_pulse;
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wire rd_en = rd_pulse;
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wire rd_en = rd_pulse;
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wire [15:2] addr_in = addr_latch[15:2];
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wire [31:0] addr_in = addr_latch[31:0];
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wire [31:0] data_in = data_latch;
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wire [31:0] data_in = data_latch;
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up_monitor inst (
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up_monitor inst (
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.clk(clk),
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.clk(clk),
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.wr_en(wr_en),
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.wr_en(wr_en),
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.rd_en(rd_en),
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.rd_en(rd_en),
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.addr_in(addr_in),
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.addr_in(addr_in),
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.data_in(data_in),
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.data_in(data_in),
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.icontrol0(CHIPSCOPE_ICON_CONTROL0),
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.icontrol0(CHIPSCOPE_ICON_CONTROL0),
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.icontrol1(CHIPSCOPE_ICON_CONTROL1),
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.icontrol1(CHIPSCOPE_ICON_CONTROL1),
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.icontrol2(CHIPSCOPE_ICON_CONTROL2)
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.icontrol2(CHIPSCOPE_ICON_CONTROL2)
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);
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);
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endmodule
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endmodule
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