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[/] [bustap-jtag/] [trunk/] [sim/] [reg_bfm_sv.v] - Diff between revs 9 and 15
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//**************************************************************
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//**************************************************************
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// Module : reg_bfm_sv.v
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// Module : reg_bfm_sv.v
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// Platform : Windows xp sp2
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// Platform : Windows xp sp2
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// Simulator : Modelsim 6.5b
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// Simulator : Modelsim 6.5b
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// Synthesizer :
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// Synthesizer :
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// Place and Route :
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// Place and Route :
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// Targets device :
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// Targets device :
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Organization : www.opencores.org
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// Revision : 2.1
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// Revision : 2.2
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// Date : 2012/03/19
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// Date : 2012/03/28
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// Description : Register BFM
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// Description : Register BFM
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//**************************************************************
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//**************************************************************
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module reg_bfm_sv (
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module reg_bfm_sv (
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input up_clk,
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input up_clk,
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input up_wbe,up_csn, // negative logic
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input up_wbe,up_csn, // negative logic
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input [15:0] up_addr,
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input [15:0] up_addr,
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inout [31:0] up_data_io
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inout [31:0] up_data_io
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);
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);
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wire [31:0] up_data_i;
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wire [31:0] up_data_i;
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reg [31:0] up_data_o;
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reg [31:0] up_data_o;
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assign #10 up_data_io = (up_wbe&&!up_csn)? up_data_o : 32'bzzzzzzzz;
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assign #10 up_data_io = (up_wbe&&!up_csn)? up_data_o : 32'bzzzzzzzz;
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assign up_data_i = up_data_io;
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assign up_data_i = up_data_io;
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reg [31:0] RAM [0:3];
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reg [31:0] RAM [0:3];
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always @(posedge up_clk) begin
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always @(posedge up_clk) begin
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if (!up_wbe && !up_csn)
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if (!up_wbe && !up_csn)
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RAM[up_addr[3:2]] <= up_data_i;
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RAM[up_addr[3:2]] <= up_data_i;
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up_data_o <= RAM[up_addr[3:2]];
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up_data_o <= RAM[up_addr[3:2]];
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end
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end
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endmodule
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endmodule
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