//**************************************************************
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//**************************************************************
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// Module : up_monitor_tb.v
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// Module : up_monitor_tb.v
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// Platform : Windows xp sp2
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// Platform : Windows xp sp2
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// Simulator : Modelsim 6.5b
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// Simulator : Modelsim 6.5b
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// Synthesizer :
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// Synthesizer :
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// Place and Route :
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// Place and Route :
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// Targets device :
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// Targets device :
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Organization : www.opencores.org
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// Revision : 2.1
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// Revision : 2.2
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// Date : 2012/03/19
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// Date : 2012/03/28
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// Description : up_monitor testbench at both pin level
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// Description : up_monitor testbench at both pin level
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// and transaction level
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// and transaction level
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//**************************************************************
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//**************************************************************
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module up_monitor_tb ();
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module up_monitor_tb ();
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reg cpu_start;
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reg cpu_start;
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reg up_clk;
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reg up_clk;
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wire up_wbe, up_csn;
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wire up_wbe, up_csn;
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wire [15:2] up_addr;
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wire [15:2] up_addr;
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wire [31:0] up_data_io;
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wire [31:0] up_data_io;
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initial begin
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initial begin
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up_clk = 1'b0;
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up_clk = 1'b0;
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forever #5 up_clk = !up_clk;
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forever #5 up_clk = !up_clk;
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end
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end
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// pin level DUT
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// pin level DUT
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up_monitor_wrapper MON_LO (
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up_monitor_wrapper MON_LO (
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.up_clk(up_clk),
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.up_clk(up_clk),
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.up_wbe(), // negative logic
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.up_wbe(), // negative logic
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.up_csn(), // negative logic
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.up_csn(), // negative logic
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.up_addr(),
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.up_addr(),
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.up_data_io()
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.up_data_io()
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);
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);
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up_bfm_sv CPU (
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up_bfm_sv CPU (
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.up_clk(up_clk),
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.up_clk(up_clk),
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.up_wbe(up_wbe), // negative logic
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.up_wbe(up_wbe), // negative logic
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.up_csn(up_csn), // negative logic
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.up_csn(up_csn), // negative logic
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.up_addr(up_addr),
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.up_addr(up_addr),
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.up_data_io(up_data_io)
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.up_data_io(up_data_io)
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);
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);
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reg_bfm_sv REG (
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reg_bfm_sv REG (
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.up_clk(up_clk),
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.up_clk(up_clk),
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.up_wbe(up_wbe), // negative logic
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.up_wbe(up_wbe), // negative logic
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.up_csn(up_csn), // negative logic
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.up_csn(up_csn), // negative logic
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.up_addr({up_addr,2'b00}),
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.up_addr({up_addr,2'b00}),
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.up_data_io(up_data_io)
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.up_data_io(up_data_io)
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);
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);
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jtag_bfm_sv JTAG (
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jtag_bfm_sv JTAG (
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);
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);
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assign MON_LO.up_wbe = up_wbe;
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assign MON_LO.up_wbe = up_wbe;
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assign MON_LO.up_csn = up_csn;
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assign MON_LO.up_csn = up_csn;
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assign MON_LO.up_addr = up_addr;
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assign MON_LO.up_addr = up_addr;
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assign MON_LO.up_data_io = up_data_io;
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assign MON_LO.up_data_io = up_data_io;
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initial begin
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initial begin
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up_monitor_tb.CPU.up_start = 0;
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up_monitor_tb.CPU.up_start = 0;
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@(posedge up_monitor_tb.JTAG.jtag_sim_done);
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@(posedge up_monitor_tb.JTAG.jtag_sim_done);
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up_monitor_tb.CPU.up_start = 1;
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up_monitor_tb.CPU.up_start = 1;
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#100000000 $stop;
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#100000000 $stop;
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end
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end
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endmodule
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endmodule
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