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(.) Tj
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0.0514 Tc 0 Tw (memory/makemem) Tj
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0.192 Tc -0.288 Tw (, an intel hex file ) Tj
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0 Tc (\).) Tj
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-0.048 Tc 0.168 Tw (LOAD >) Tj
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0.084 Tc 0.0189 Tw (After the base system containing the loader is working, you can develop your own applications.) Tj
-5.76 -13.92 TD 0.0454 Tc -0.114 Tw (Two applications are provided with the CPU: ) Tj
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0.03 Tc 0 Tw (test) Tj
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20.16 0 TD /F1 12 Tf
(.) Tj
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144.48 0 TD /F0 12 Tf
-0.03 Tc 0 Tw (test.ihx) Tj
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5.76 -19.92 TD 0.1829 Tc -0.3269 Tw (I was initially using the ) Tj
115.2 0 TD /F0 12 Tf
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-201.6 -14.16 TD 0.0431 Tc -0.269 Tw (hex\) files to the FPGA was very slow \(even though the baud rate was 115,200\). Therefore I wrote) Tj
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421.44 0 TD /F0 12 Tf
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190.56 0 TD /F0 12 Tf
0.08 Tc 0 Tw (cmd) Tj
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-212.64 -14.16 TD 0.0313 Tc -0.1753 Tw (a window. tty is started as:) Tj
28.32 -19.92 TD /F0 12 Tf
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0 Tc 0 Tw ( ) Tj
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0.08 Tc (tty) Tj
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0.024 Tc 0 Tw (COM1:) Tj
39.36 0 TD /F1 12 Tf
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0.08 Tc 0 Tw (cmd) Tj
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110.88 0 TD /F0 12 Tf
-0.06 Tc 0 Tw (^L) Tj
14.88 0 TD /F1 12 Tf
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0 Tc (.) Tj
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0.12 Tc (3) Tj
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-0.04 Tc (infile) Tj
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-0.04 Tc 1.6 Tw (. The -l) Tj
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T* 0.072 Tc -0.072 Tw (external SRAM is used\).) Tj
-79.2 -20.16 TD /F0 12 Tf
0.03 Tc 0 Tw (Limitations:) Tj
79.2 0 TD /F1 12 Tf
-0.045 Tc -0.035 Tw (Not too well tested) Tj
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0.02 Tc 0 Tw (struct) Tj
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22.08 0 TD /F1 12 Tf
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-0.04 Tc 0 Tw (3.2) Tj
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-0.0133 Tc (Synopsis:) Tj
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-79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj
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0.1366 Tc 0.8418 Tw (Assemble and link the input assembler file and create \(1\) a binary output file) Tj
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169.44 0 TD /F0 12 Tf
0.0343 Tc 0 Tw (makemem) Tj
53.28 0 TD /F1 12 Tf
0.1239 Tc 0.699 Tw ( utility\), \(2\) a list file \(useful for) Tj
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0 -13.92 TD 0.1389 Tc -0.2932 Tw (symbols in a nice way\), and \(4\) an intel hex file \(used by the loader\).) Tj
-79.2 -20.16 TD /F0 12 Tf
0 Tc 0 Tw (Limitations) Tj
59.28 0 TD /F1 12 Tf
(:) Tj
19.92 0 TD 0.1565 Tc -0.2765 Tw (Can not link several files.) Tj
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-157.68 -20.16 TD /F0 12 Tf
0 Tc 0 Tw (Limitations) Tj
59.28 0 TD /F1 12 Tf
(:) Tj
19.92 0 TD 0.0768 Tc -0.3168 Tw (Can not simulate interrupts.) Tj
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0.0857 Tc 0 Tw (Comment) Tj
50.64 0 TD /F1 12 Tf
0 Tc (:) Tj
28.56 0 TD 0.1075 Tc -0.1293 Tw (The simulator is useful for debugging the compiler and assembler. If something) Tj
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0 -14.16 TD 0.0494 Tc -0.3044 Tw (then the error is in the hardware \(vhdl\). If it does not work in the simulator, then) Tj
0 -13.92 TD 0.1 Tc -0.292 Tw (the error is in the compiler.) Tj
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0.024 Tc 0 Tw (COM1:) Tj
39.36 0 TD /F1 12 Tf
0.048 Tc -0.108 Tw (. The special character ) Tj
110.88 0 TD /F0 12 Tf
-0.06 Tc 0 Tw (^L) Tj
14.88 0 TD /F1 12 Tf
0.08 Tc -0.2 Tw ( causes ) Tj
37.2 0 TD /F0 12 Tf
0 Tc 0 Tw (tty) Tj
13.92 0 TD /F1 12 Tf
0.0554 Tc -0.0954 Tw ( to copy the file ) Tj
81.12 0 TD /F0 12 Tf
0.0133 Tc 0.1067 Tw (filename \() Tj
50.88 0 TD /F1 12 Tf
-0.12 Tc 0.12 Tw (or ) Tj
12.96 0 TD /F0 12 Tf
-0.015 Tc 0 Tw (rtos.ihx) Tj
39.12 0 TD /F1 12 Tf
0.3 Tc -0.54 Tw ( if no) Tj
-442.8 -14.16 TD 0.24 Tc 0 Tw (filename) Tj
42 0 TD /F0 12 Tf
0 Tc 0.12 Tw ( ) Tj
2.88 0 TD /F1 12 Tf
0.0891 Tc -0.1791 Tw (is provided as a command line argument\) to ) Tj
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0.024 Tc 0 Tw (COM1:) Tj
39.36 0 TD /F1 12 Tf
0 Tc (.) Tj
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0.12 Tc (3) Tj
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-56.64 -31.2 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (3.1) Tj
56.64 0 TD 0.0512 Tc 0.0688 Tw (C Compiler) Tj
-50.88 -18.72 TD /F0 12 Tf
-0.0133 Tc 0 Tw (Synopsis:) Tj
79.2 0 TD 0.0207 Tc -0.0507 Tw (cc80 [ -l ] memtop infile [ outfile ]) Tj
-79.2 -19.92 TD 0.0267 Tc 0.0933 Tw (Example 1:) Tj
79.2 0 TD 0 Tc 0.06 Tw (cc80 -l 0x2000 loader.c loader.asm) Tj
-79.2 -20.16 TD 0.0267 Tc 0.0933 Tw (Example 2:) Tj
79.2 0 TD 0.005 Tc 0.035 Tw (cc80 0x2000 rtos.c rtos.asm) Tj
-79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj
79.2 0 TD /F1 12 Tf
0.1143 Tc 1.3857 Tw (Compile the C source file) Tj
0 Tc 0 Tw ( ) Tj
134.16 0 TD /F0 12 Tf
-0.04 Tc (infile) Tj
26.16 0 TD /F1 12 Tf
0.1152 Tc 1.3728 Tw ( and create the assembler file) Tj
0 Tc 0 Tw ( ) Tj
151.92 0 TD /F0 12 Tf
-0.0171 Tc (outfile) Tj
32.64 0 TD /F1 12 Tf
-0.04 Tc 1.6 Tw (. The -l) Tj
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0 -13.92 TD 0.0662 Tc 0.783 Tw (instance, 0x2000 = 8k for FPGA internal memory, or 0xA000 = 40k when an) Tj
T* 0.072 Tc -0.072 Tw (external SRAM is used\).) Tj
-79.2 -20.16 TD /F0 12 Tf
0.03 Tc 0 Tw (Limitations:) Tj
79.2 0 TD /F1 12 Tf
-0.045 Tc -0.035 Tw (Not too well tested) Tj
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0.02 Tc 0 Tw (struct) Tj
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22.08 0 TD /F1 12 Tf
-0.03 Tc 0.03 Tw ( data type) Tj
-39.84 -20.16 TD 0.0835 Tc -0.2168 Tw (Name should be cc16 \(a left-over from the Z80 compiler\)) Tj
-84.96 -29.28 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (3.2) Tj
56.64 0 TD 0.0576 Tc (Assembler) Tj
-50.88 -18.72 TD /F0 12 Tf
-0.0133 Tc (Synopsis:) Tj
79.2 0 TD -0.0115 Tc 0.0515 Tw (assembler infile [ binfile [ listfile[ symfile [ ihxfile ] ] ] ]) Tj
-79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj
79.2 0 TD 0.0144 Tc -0.0144 Tw (assembler rtos.asm rtos.bin) Tj
-79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj
79.2 0 TD /F1 12 Tf
0.1366 Tc 0.8418 Tw (Assemble and link the input assembler file and create \(1\) a binary output file) Tj
0 -14.16 TD 0.0978 Tc 0.5879 Tw (\(used by the simulator and by the ) Tj
169.44 0 TD /F0 12 Tf
0.0343 Tc 0 Tw (makemem) Tj
53.28 0 TD /F1 12 Tf
0.1239 Tc 0.699 Tw ( utility\), \(2\) a list file \(useful for) Tj
-222.72 -13.92 TD 0.1088 Tc 1.6112 Tw (debugging\), \(3\) a symbol file \(used by the simulator to display source level) Tj
0 -13.92 TD 0.1389 Tc -0.2932 Tw (symbols in a nice way\), and \(4\) an intel hex file \(used by the loader\).) Tj
-79.2 -20.16 TD /F0 12 Tf
0 Tc 0 Tw (Limitations) Tj
59.28 0 TD /F1 12 Tf
(:) Tj
19.92 0 TD 0.1565 Tc -0.2765 Tw (Can not link several files.) Tj
-84.96 -29.28 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (3.3) Tj
56.64 0 TD 0.0624 Tc (Simulator) Tj
-50.88 -18.72 TD /F0 12 Tf
-0.0133 Tc (Synopsis:) Tj
79.2 0 TD -0.0055 Tc 0.0055 Tw (simulate binfile symfile) Tj
-79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj
79.2 0 TD 0.015 Tc -0.135 Tw (simulate test.bin test.sym) Tj
-79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj
79.2 0 TD /F1 12 Tf
0.15 Tc -0.15 Tw (Simulate ) Tj
45.84 0 TD /F0 12 Tf
-0.0343 Tc 0 Tw (binfile) Tj
32.64 0 TD /F1 12 Tf
0.0884 Tc -0.1684 Tw ( at instruction level.) Tj
-157.68 -20.16 TD /F0 12 Tf
0 Tc 0 Tw (Limitations) Tj
59.28 0 TD /F1 12 Tf
(:) Tj
19.92 0 TD 0.0768 Tc -0.3168 Tw (Can not simulate interrupts.) Tj
-79.2 -19.92 TD /F0 12 Tf
0.0857 Tc 0 Tw (Comment) Tj
50.64 0 TD /F1 12 Tf
0 Tc (:) Tj
28.56 0 TD 0.1075 Tc -0.1293 Tw (The simulator is useful for debugging the compiler and assembler. If something) Tj
0 -13.92 TD 0.0517 Tc 0.7323 Tw (does not work, check if it works in the simulator. If it works in the simulator,) Tj
0 -14.16 TD 0.0494 Tc -0.3044 Tw (then the error is in the hardware \(vhdl\). If it does not work in the simulator, then) Tj
0 -13.92 TD 0.1 Tc -0.292 Tw (the error is in the compiler.) Tj
ET
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/F0 13.92 Tf
-0.04 Tc 0 Tw (3.4) Tj
56.64 0 TD 0.0974 Tc (Makemem) Tj
-50.88 -18.72 TD /F0 12 Tf
-0.0133 Tc (Synopsis:) Tj
79.2 0 TD 0.0171 Tc 0.1029 Tw (makemem binfile) Tj
-79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj
79.2 0 TD 0.0212 Tc 0.0988 Tw (makemem loader.bin) Tj
-79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj
79.2 0 TD /F1 12 Tf
0 Tc (Create ) Tj
34.32 0 TD /F0 12 Tf
0.0052 Tc (../vhdl/mem_content.vhd) Tj
126.96 0 TD /F1 12 Tf
0.18 Tc -0.3 Tw ( from ) Tj
29.28 0 TD /F0 12 Tf
-0.0343 Tc 0 Tw (binfile) Tj
32.64 0 TD /F1 12 Tf
0 Tc (.) Tj
-302.4 -20.16 TD /F0 12 Tf
(Limitations) Tj
59.28 0 TD /F1 12 Tf
(:) Tj
19.92 0 TD 0.1239 Tc 0.91 Tw (Output file name should be a command line argument rather than a fixed file) Tj
0 -13.92 TD 0.18 Tc 0 Tw (name) Tj
-84.96 -29.28 TD /F0 13.92 Tf
-0.04 Tc (3.5) Tj
56.64 0 TD 0 Tc (Tty) Tj
-50.88 -18.72 TD /F0 12 Tf
-0.0133 Tc (Synopsis:) Tj
79.2 0 TD -0.024 Tc 0.144 Tw (tty ihxfile) Tj
-79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj
79.2 0 TD -0.0327 Tc 0.1527 Tw (tty rtos.ihx) Tj
-79.2 -20.16 TD 0.0267 Tc 0 Tw (Function:) Tj
79.2 0 TD /F1 12 Tf
0.0893 Tc -0.1579 Tw (Terminal program for Windows. Typing ^L downloads ) Tj
268.08 0 TD /F0 12 Tf
-0.0343 Tc 0 Tw (ihxfile) Tj
32.16 0 TD /F1 12 Tf
0 Tc (.) Tj
-379.44 -19.92 TD /F0 12 Tf
(Limitations) Tj
59.28 0 TD /F1 12 Tf
(:) Tj
19.92 0 TD 0.0429 Tc -0.2029 Tw (Baudrate is fixed to 115, 200 Baud) Tj
0 -19.92 TD 0.0267 Tc -0.1139 Tw (Data foirmat fixed to 8 data bits, 1 stop bit, no parity) Tj
-84.96 -29.52 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (3.6) Tj
56.64 0 TD 0.0368 Tc (Bin2array) Tj
-50.88 -18.48 TD /F0 12 Tf
-0.0133 Tc (Synopsis:) Tj
79.2 0 TD -0.015 Tc -0.105 Tw (bin2array binfile) Tj
-79.2 -20.16 TD 0.03 Tc 0 Tw (Example:) Tj
79.2 0 TD 0.0063 Tc -0.1263 Tw (bin2array loader.bin) Tj
-79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj
79.2 0 TD /F1 12 Tf
0.0761 Tc -0.2132 Tw (Writes a C array respresnting binfile to stdout.) Tj
-79.2 -19.92 TD /F0 12 Tf
0.0857 Tc 0 Tw (Comment) Tj
50.64 0 TD /F1 12 Tf
0 Tc (:) Tj
28.56 0 TD 0.0812 Tc 0.2327 Tw (Useful for e.g. providing a loader in an application, so that one application can) Tj
0 -14.16 TD 0.0542 Tc -0.1502 Tw (load another application. See array ) Tj
169.92 0 TD /F0 12 Tf
0.03 Tc 0 Tw (loader[]) Tj
40.56 0 TD /F1 12 Tf
0.08 Tc -0.176 Tw ( in rtos.c for an example.) Tj
-295.44 -36 TD /F0 18 Tf
0.12 Tc 0 Tw (4) Tj
56.64 0 TD -0.0095 Tc 0.0695 Tw (Hardware Description) Tj
-56.64 -31.2 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (4.1) Tj
56.64 0 TD 0.0107 Tc (board_cpu.vhd) Tj
-50.88 -18.72 TD /F1 12 Tf
0.1629 Tc -0.3229 Tw (This is the top level design file.) Tj
0 -19.92 TD 0.06 Tc -0.1708 Tw (Adaptations to other boards that the Avnet board should be made in this file.) Tj
0 -20.16 TD 0.1357 Tc -0.2557 Tw (Essentially instantiates ) Tj
112.56 0 TD /F0 12 Tf
-0.0133 Tc 0 Tw (cpu16.vhd) Tj
53.04 0 TD /F1 12 Tf
0 Tc (.) Tj
-171.36 -29.28 TD /F0 13.92 Tf
-0.04 Tc (4.2) Tj
56.64 0 TD 0.0016 Tc (cpu16.vhd) Tj
-50.88 -18.72 TD /F1 12 Tf
0.0519 Tc -0.1586 Tw (Breaks down the system on a chip into 3 parts:) Tj
50.88 -19.92 TD -2.64 Tc 0 Tw (\225) Tj
56.64 0 TD /F0 12 Tf
-0.0086 Tc (cpu_engine.vhd) Tj
80.4 0 TD /F1 12 Tf
-0.24 Tc 0.24 Tw (. ) Tj
33.12 0 TD 0.1171 Tc -0.5704 Tw (This module is the CPU itself, plus 8kByte onchip ) Tj
0 -13.92 TD 0.12 Tc 0 Tw (RAM.) Tj
-170.16 -14.16 TD -2.64 Tc (\225) Tj
56.64 0 TD /F0 12 Tf
-0.015 Tc (input_output.vhd) Tj
89.76 0 TD /F1 12 Tf
0 Tc ( ) Tj
23.76 0 TD 0.0821 Tc -0.2021 Tw (This module contains the I/O functions of the ) Tj
0 -13.92 TD 0.0324 Tc -0.1224 Tw (Avnet board. You need to rewrite this module ) Tj
T* 0.0726 Tc -0.2326 Tw (\(and possibly the applications\) for other boards.) Tj
-170.16 -14.16 TD -2.64 Tc 0 Tw (\225) Tj
56.64 0 TD /F0 12 Tf
0 Tc (bin_to_7segment.vhd) Tj
108.96 0 TD /F1 12 Tf
0.0743 Tc -0.1343 Tw (. This module contains a driver that continuously ) Tj
4.56 -13.92 TD 0.0585 Tc -0.3285 Tw (displays the program counter of the CPU. Usefule ) Tj
0 -13.92 TD 0.091 Tc -0.211 Tw (for debugging the system on a chip.) Tj
ET
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BT
72 710.64 TD
0 0 0 rg
/F0 13.92 Tf
-0.04 Tc 0 Tw (3.4) Tj
56.64 0 TD 0.0974 Tc (Makemem) Tj
-50.88 -18.72 TD /F0 12 Tf
-0.0133 Tc (Synopsis:) Tj
79.2 0 TD 0.0171 Tc 0.1029 Tw (makemem binfile) Tj
-79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj
79.2 0 TD 0.0212 Tc 0.0988 Tw (makemem loader.bin) Tj
-79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj
79.2 0 TD /F1 12 Tf
0 Tc (Create ) Tj
34.32 0 TD /F0 12 Tf
0.0052 Tc (../vhdl/mem_content.vhd) Tj
126.96 0 TD /F1 12 Tf
0.18 Tc -0.3 Tw ( from ) Tj
29.28 0 TD /F0 12 Tf
-0.0343 Tc 0 Tw (binfile) Tj
32.64 0 TD /F1 12 Tf
0 Tc (.) Tj
-302.4 -20.16 TD /F0 12 Tf
(Limitations) Tj
59.28 0 TD /F1 12 Tf
(:) Tj
19.92 0 TD 0.1239 Tc 0.91 Tw (Output file name should be a command line argument rather than a fixed file) Tj
0 -13.92 TD 0.18 Tc 0 Tw (name) Tj
-84.96 -29.28 TD /F0 13.92 Tf
-0.04 Tc (3.5) Tj
56.64 0 TD 0 Tc (Tty) Tj
-50.88 -18.72 TD /F0 12 Tf
-0.0133 Tc (Synopsis:) Tj
79.2 0 TD -0.024 Tc 0.144 Tw (tty ihxfile) Tj
-79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj
79.2 0 TD -0.0327 Tc 0.1527 Tw (tty rtos.ihx) Tj
-79.2 -20.16 TD 0.0267 Tc 0 Tw (Function:) Tj
79.2 0 TD /F1 12 Tf
0.0893 Tc -0.1579 Tw (Terminal program for Windows. Typing ^L downloads ) Tj
268.08 0 TD /F0 12 Tf
-0.0343 Tc 0 Tw (ihxfile) Tj
32.16 0 TD /F1 12 Tf
0 Tc (.) Tj
-379.44 -19.92 TD /F0 12 Tf
(Limitations) Tj
59.28 0 TD /F1 12 Tf
(:) Tj
19.92 0 TD 0.0429 Tc -0.2029 Tw (Baudrate is fixed to 115, 200 Baud) Tj
0 -19.92 TD 0.0267 Tc -0.1139 Tw (Data foirmat fixed to 8 data bits, 1 stop bit, no parity) Tj
-84.96 -29.52 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (3.6) Tj
56.64 0 TD 0.0368 Tc (Bin2array) Tj
-50.88 -18.48 TD /F0 12 Tf
-0.0133 Tc (Synopsis:) Tj
79.2 0 TD -0.015 Tc -0.105 Tw (bin2array binfile) Tj
-79.2 -20.16 TD 0.03 Tc 0 Tw (Example:) Tj
79.2 0 TD 0.0063 Tc -0.1263 Tw (bin2array loader.bin) Tj
-79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj
79.2 0 TD /F1 12 Tf
0.0761 Tc -0.2132 Tw (Writes a C array respresnting binfile to stdout.) Tj
-79.2 -19.92 TD /F0 12 Tf
0.0857 Tc 0 Tw (Comment) Tj
50.64 0 TD /F1 12 Tf
0 Tc (:) Tj
28.56 0 TD 0.0812 Tc 0.2327 Tw (Useful for e.g. providing a loader in an application, so that one application can) Tj
0 -14.16 TD 0.0542 Tc -0.1502 Tw (load another application. See array ) Tj
169.92 0 TD /F0 12 Tf
0.03 Tc 0 Tw (loader[]) Tj
40.56 0 TD /F1 12 Tf
0.08 Tc -0.176 Tw ( in rtos.c for an example.) Tj
-295.44 -36 TD /F0 18 Tf
0.12 Tc 0 Tw (4) Tj
56.64 0 TD -0.0095 Tc 0.0695 Tw (Hardware Description) Tj
-56.64 -31.2 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (4.1) Tj
56.64 0 TD 0.0107 Tc (board_cpu.vhd) Tj
-50.88 -18.72 TD /F1 12 Tf
0.1629 Tc -0.3229 Tw (This is the top level design file.) Tj
0 -19.92 TD 0.06 Tc -0.1708 Tw (Adaptations to other boards that the Avnet board should be made in this file.) Tj
0 -20.16 TD 0.1357 Tc -0.2557 Tw (Essentially instantiates ) Tj
112.56 0 TD /F0 12 Tf
-0.0133 Tc 0 Tw (cpu16.vhd) Tj
53.04 0 TD /F1 12 Tf
0 Tc (.) Tj
-171.36 -29.28 TD /F0 13.92 Tf
-0.04 Tc (4.2) Tj
56.64 0 TD 0.0016 Tc (cpu16.vhd) Tj
-50.88 -18.72 TD /F1 12 Tf
0.0519 Tc -0.1586 Tw (Breaks down the system on a chip into 3 parts:) Tj
50.88 -19.92 TD -2.64 Tc 0 Tw (\225) Tj
56.64 0 TD /F0 12 Tf
-0.0086 Tc (cpu_engine.vhd) Tj
80.4 0 TD /F1 12 Tf
-0.24 Tc 0.24 Tw (. ) Tj
33.12 0 TD 0.1171 Tc -0.5704 Tw (This module is the CPU itself, plus 8kByte onchip ) Tj
0 -13.92 TD 0.12 Tc 0 Tw (RAM.) Tj
-170.16 -14.16 TD -2.64 Tc (\225) Tj
56.64 0 TD /F0 12 Tf
-0.015 Tc (input_output.vhd) Tj
89.76 0 TD /F1 12 Tf
0 Tc ( ) Tj
23.76 0 TD 0.0821 Tc -0.2021 Tw (This module contains the I/O functions of the ) Tj
0 -13.92 TD 0.0324 Tc -0.1224 Tw (Avnet board. You need to rewrite this module ) Tj
T* 0.0726 Tc -0.2326 Tw (\(and possibly the applications\) for other boards.) Tj
-170.16 -14.16 TD -2.64 Tc 0 Tw (\225) Tj
56.64 0 TD /F0 12 Tf
0 Tc (bin_to_7segment.vhd) Tj
108.96 0 TD /F1 12 Tf
0.0743 Tc -0.1343 Tw (. This module contains a driver that continuously ) Tj
4.56 -13.92 TD 0.0585 Tc -0.3285 Tw (displays the program counter of the CPU. Usefule ) Tj
0 -13.92 TD 0.091 Tc -0.211 Tw (for debugging the system on a chip.) Tj
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BT
72 710.64 TD
0 0 0 rg
/F0 13.92 Tf
-0.04 Tc 0 Tw (4.3) Tj
56.64 0 TD 0.0298 Tc (bin_to_7segment.vhd) Tj
-50.88 -18.72 TD /F1 12 Tf
0.098 Tc 1.2353 Tw (This module samples the PC of the CPU at fixed intervals and shows the value on a pair of) Tj
-5.76 -13.92 TD 0.0752 Tc -0.1752 Tw (7segment LEDs. This function is specific to the Avnet board providing the LEDs.) Tj
0 -29.28 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (4.4) Tj
56.64 0 TD 0 Tc (input_output.vhd) Tj
-50.88 -18.72 TD /F1 12 Tf
0.0658 Tc 1.0142 Tw (This module provids a number of I/O functions that can be accessed by the CPU through the) Tj
-5.76 -13.92 TD 0.1029 Tc -0.3429 Tw (assembler instructions) Tj
84.96 -20.16 TD /F0 12 Tf
0.06 Tc 0.06 Tw (IN ) Tj
56.88 0 TD 0.0267 Tc -0.1467 Tw (\(port\), RU) Tj
113.28 0 TD /F1 12 Tf
0.08 Tc 0 Tw (and) Tj
-170.16 -19.92 TD /F0 12 Tf
-0.04 Tc (OUT) Tj
56.88 0 TD 0.06 Tc -0.18 Tw (R, \(port\)) Tj
-136.08 -19.92 TD /F1 12 Tf
0.0835 Tc -0.2435 Tw (The ports implemented are:) Tj
152.16 -52.08 TD -0.04 Tc 0.04 Tw (Port Function) Tj
238.56 0 TD -0.12 Tc 0 Tw (IN) Tj
36 0 TD 0 Tc (OUT) Tj
-426.48 -24 TD /F0 12 Tf
(IN_RX_DATA) Tj
76.56 0 TD /F1 12 Tf
0.0226 Tc -0.219 Tw (: Data to be transmitted on serial output. In polled operation, ) Tj
-76.56 -13.92 TD 0.0514 Tc -0.5314 Tw (you need to check ) Tj
88.08 0 TD /F0 12 Tf
-0.0133 Tc 0 Tw (IN_STATUS) Tj
66 0 TD /F1 12 Tf
0.0431 Tc -0.4931 Tw ( before sending data. Reading this port resets ) Tj
-154.08 -14.16 TD 0.1309 Tc -0.2269 Tw (bits 4 and 0 in ) Tj
71.04 0 TD /F0 12 Tf
0.0133 Tc 0 Tw (IN_STATUS) Tj
66 0 TD /F1 12 Tf
0 Tc (.) Tj
244.56 28.08 TD (0) Tj
-381.6 -49.92 TD /F0 12 Tf
-0.0133 Tc (IN_STATUS) Tj
66 0 TD /F1 12 Tf
0.0462 Tc -0.1262 Tw (: Status of serial I/O and timer) Tj
-66 -14.16 TD 0.016 Tc -0.196 Tw (Bit 7: not used \(0\)) Tj
0 -13.92 TD 0.0758 Tc -0.2067 Tw (Bit 6: 1 iff timer interrupt enabled and timer interrupt has occured) Tj
T* 0.0876 Tc -0.2248 Tw (Bit 5:1 iff serial Tx interrupt enabled and serial Tx is ready to accept data) Tj
0 -14.16 TD 0.1163 Tc -0.227 Tw (Bit 4:1 iff serial Rx interrupt enabled and serial Rx has received valid data) Tj
0 -13.92 TD 0.015 Tc -0.195 Tw (Bit 3: :not used \(0\)) Tj
T* 0.08 Tc -0.28 Tw (Bit 2:1 iff timer interrupt has occured) Tj
0 -14.16 TD 0.0754 Tc -0.1654 Tw (Bit 1:iff serial Tx is ready to accept data) Tj
0 -13.92 TD 0.1362 Tc -0.2862 Tw (Bit 0:1 iff serial Rx has received valid data) Tj
381.6 112.08 TD 0 Tc 0 Tw (1) Tj
-381.6 -134.16 TD /F0 12 Tf
-0.0109 Tc (IN_TEMPERAT) Tj
87.36 0 TD /F1 12 Tf
0.036 Tc -0.126 Tw (: current value from temperature sensor \(8 bit 2) Tj
-2.64 Tc 0 Tw (\222) Tj
0.09 Tc -0.09 Tw (s comple-) Tj
-87.36 -13.92 TD 0.1054 Tc -0.2254 Tw (ment in degrees Celsius\) \(Avnet board specific\)) Tj
381.6 13.92 TD 0 Tc 0 Tw (2) Tj
-381.6 -36 TD /F0 12 Tf
(IN_DIP_SWITCH) Tj
95.28 0 TD /F1 12 Tf
0.0528 Tc -0.4261 Tw (: current setting of the DIP switch. \(Avnet board specific\)) Tj
286.32 0 TD 0 Tc 0 Tw (3) Tj
-381.6 -21.84 TD /F0 12 Tf
-0.0086 Tc (IN_CLK_CTR_LOW) Tj
111.84 0 TD /F1 12 Tf
0.0457 Tc -0.1657 Tw (: current value of a 16 bit clock counter \(low byte\)) Tj
269.76 0 TD 0 Tc 0 Tw (4) Tj
-381.6 -22.08 TD /F0 12 Tf
(IN_CLK_CTR_HIGH) Tj
115.2 0 TD /F1 12 Tf
0.067 Tc -0.2197 Tw (: current value of a 16 bit clock counter \(high byte\)) Tj
266.4 0 TD 0 Tc 0 Tw (5) Tj
-381.6 -22.08 TD /F0 12 Tf
-0.0109 Tc (OUT_TX_DATA) Tj
88.56 0 TD /F1 12 Tf
0.07 Tc -0.238 Tw (: Data received on serial input. In polled operation, you ) Tj
-88.56 -13.92 TD 0 Tc 0 Tw (need to check ) Tj
68.88 0 TD /F0 12 Tf
-0.0133 Tc (IN_STATUS) Tj
66 0 TD /F1 12 Tf
0.054 Tc -0.1607 Tw ( before readiing data. Writing this port resets ) Tj
-134.88 -13.92 TD 0.1309 Tc -0.2269 Tw (bits 5 and 1 in ) Tj
71.04 0 TD /F0 12 Tf
0.0133 Tc 0 Tw (IN_STATUS) Tj
66 0 TD /F1 12 Tf
0 Tc (.) Tj
287.04 27.84 TD (0) Tj
-424.08 -49.92 TD /F0 12 Tf
-0.0343 Tc 0.1543 Tw (not used) Tj
424.08 0 TD /F1 12 Tf
0 Tc 0 Tw (1) Tj
-424.08 -22.08 TD /F0 12 Tf
-0.015 Tc (OUT_LEDS) Tj
63.36 0 TD /F1 12 Tf
0.0261 Tc -0.1461 Tw (: Turns each of the 8 LEDs on or off. 1 turns LED on.\(Avnet ) Tj
-63.36 -13.92 TD 0.1029 Tc -0.3429 Tw (board specific\)) Tj
424.08 13.92 TD 0 Tc 0 Tw (2) Tj
ET
71.76 100.32 0.48 419.52 re f
453.36 99.84 0.48 420.48 re f
495.84 99.84 0.48 420.48 re f
537.12 100.32 0.48 419.52 re f
71.76 520.32 m
71.76 519.84 l
537.6 519.84 l
537.6 520.32 l
h
f
72.24 495.6 m
72.24 495.12 l
537.12 495.12 l
537.12 495.6 l
h
f
72.24 492.96 m
72.24 492.48 l
537.12 492.48 l
537.12 492.96 l
h
f
71.76 444.24 m
71.76 443.76 l
537.6 443.76 l
537.6 444.24 l
h
f
71.76 310.32 m
71.76 309.84 l
537.6 309.84 l
537.6 310.32 l
h
f
71.76 274.32 m
71.76 273.84 l
537.6 273.84 l
537.6 274.32 l
h
f
71.76 252.24 m
71.76 251.76 l
537.6 251.76 l
537.6 252.24 l
h
f
71.76 230.16 m
71.76 229.68 l
537.6 229.68 l
537.6 230.16 l
h
f
71.76 208.32 m
71.76 207.84 l
537.6 207.84 l
537.6 208.32 l
h
f
71.76 158.16 m
71.76 157.68 l
537.6 157.68 l
537.6 158.16 l
h
f
71.76 136.32 m
71.76 135.84 l
537.6 135.84 l
537.6 136.32 l
h
f
71.76 100.32 m
71.76 99.84 l
537.6 99.84 l
537.6 100.32 l
h
f
endstream
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BT
72 710.64 TD
0 0 0 rg
/F0 13.92 Tf
-0.04 Tc 0 Tw (4.3) Tj
56.64 0 TD 0.0298 Tc (bin_to_7segment.vhd) Tj
-50.88 -18.72 TD /F1 12 Tf
0.098 Tc 1.2353 Tw (This module samples the PC of the CPU at fixed intervals and shows the value on a pair of) Tj
-5.76 -13.92 TD 0.0752 Tc -0.1752 Tw (7segment LEDs. This function is specific to the Avnet board providing the LEDs.) Tj
0 -29.28 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (4.4) Tj
56.64 0 TD 0 Tc (input_output.vhd) Tj
-50.88 -18.72 TD /F1 12 Tf
0.0658 Tc 1.0142 Tw (This module provids a number of I/O functions that can be accessed by the CPU through the) Tj
-5.76 -13.92 TD 0.1029 Tc -0.3429 Tw (assembler instructions) Tj
84.96 -20.16 TD /F0 12 Tf
0.06 Tc 0.06 Tw (IN ) Tj
56.88 0 TD 0.0267 Tc -0.1467 Tw (\(port\), RU) Tj
113.28 0 TD /F1 12 Tf
0.08 Tc 0 Tw (and) Tj
-170.16 -19.92 TD /F0 12 Tf
-0.04 Tc (OUT) Tj
56.88 0 TD 0.06 Tc -0.18 Tw (R, \(port\)) Tj
-136.08 -19.92 TD /F1 12 Tf
0.0835 Tc -0.2435 Tw (The ports implemented are:) Tj
152.16 -52.08 TD -0.04 Tc 0.04 Tw (Port Function) Tj
238.56 0 TD -0.12 Tc 0 Tw (IN) Tj
36 0 TD 0 Tc (OUT) Tj
-426.48 -24 TD /F0 12 Tf
(IN_RX_DATA) Tj
76.56 0 TD /F1 12 Tf
0.0226 Tc -0.219 Tw (: Data to be transmitted on serial output. In polled operation, ) Tj
-76.56 -13.92 TD 0.0514 Tc -0.5314 Tw (you need to check ) Tj
88.08 0 TD /F0 12 Tf
-0.0133 Tc 0 Tw (IN_STATUS) Tj
66 0 TD /F1 12 Tf
0.0431 Tc -0.4931 Tw ( before sending data. Reading this port resets ) Tj
-154.08 -14.16 TD 0.1309 Tc -0.2269 Tw (bits 4 and 0 in ) Tj
71.04 0 TD /F0 12 Tf
0.0133 Tc 0 Tw (IN_STATUS) Tj
66 0 TD /F1 12 Tf
0 Tc (.) Tj
244.56 28.08 TD (0) Tj
-381.6 -49.92 TD /F0 12 Tf
-0.0133 Tc (IN_STATUS) Tj
66 0 TD /F1 12 Tf
0.0462 Tc -0.1262 Tw (: Status of serial I/O and timer) Tj
-66 -14.16 TD 0.016 Tc -0.196 Tw (Bit 7: not used \(0\)) Tj
0 -13.92 TD 0.0758 Tc -0.2067 Tw (Bit 6: 1 iff timer interrupt enabled and timer interrupt has occured) Tj
T* 0.0876 Tc -0.2248 Tw (Bit 5:1 iff serial Tx interrupt enabled and serial Tx is ready to accept data) Tj
0 -14.16 TD 0.1163 Tc -0.227 Tw (Bit 4:1 iff serial Rx interrupt enabled and serial Rx has received valid data) Tj
0 -13.92 TD 0.015 Tc -0.195 Tw (Bit 3: :not used \(0\)) Tj
T* 0.08 Tc -0.28 Tw (Bit 2:1 iff timer interrupt has occured) Tj
0 -14.16 TD 0.0754 Tc -0.1654 Tw (Bit 1:iff serial Tx is ready to accept data) Tj
0 -13.92 TD 0.1362 Tc -0.2862 Tw (Bit 0:1 iff serial Rx has received valid data) Tj
381.6 112.08 TD 0 Tc 0 Tw (1) Tj
-381.6 -134.16 TD /F0 12 Tf
-0.0109 Tc (IN_TEMPERAT) Tj
87.36 0 TD /F1 12 Tf
0.036 Tc -0.126 Tw (: current value from temperature sensor \(8 bit 2) Tj
-2.64 Tc 0 Tw (\222) Tj
0.09 Tc -0.09 Tw (s comple-) Tj
-87.36 -13.92 TD 0.1054 Tc -0.2254 Tw (ment in degrees Celsius\) \(Avnet board specific\)) Tj
381.6 13.92 TD 0 Tc 0 Tw (2) Tj
-381.6 -36 TD /F0 12 Tf
(IN_DIP_SWITCH) Tj
95.28 0 TD /F1 12 Tf
0.0528 Tc -0.4261 Tw (: current setting of the DIP switch. \(Avnet board specific\)) Tj
286.32 0 TD 0 Tc 0 Tw (3) Tj
-381.6 -21.84 TD /F0 12 Tf
-0.0086 Tc (IN_CLK_CTR_LOW) Tj
111.84 0 TD /F1 12 Tf
0.0457 Tc -0.1657 Tw (: current value of a 16 bit clock counter \(low byte\)) Tj
269.76 0 TD 0 Tc 0 Tw (4) Tj
-381.6 -22.08 TD /F0 12 Tf
(IN_CLK_CTR_HIGH) Tj
115.2 0 TD /F1 12 Tf
0.067 Tc -0.2197 Tw (: current value of a 16 bit clock counter \(high byte\)) Tj
266.4 0 TD 0 Tc 0 Tw (5) Tj
-381.6 -22.08 TD /F0 12 Tf
-0.0109 Tc (OUT_TX_DATA) Tj
88.56 0 TD /F1 12 Tf
0.07 Tc -0.238 Tw (: Data received on serial input. In polled operation, you ) Tj
-88.56 -13.92 TD 0 Tc 0 Tw (need to check ) Tj
68.88 0 TD /F0 12 Tf
-0.0133 Tc (IN_STATUS) Tj
66 0 TD /F1 12 Tf
0.054 Tc -0.1607 Tw ( before readiing data. Writing this port resets ) Tj
-134.88 -13.92 TD 0.1309 Tc -0.2269 Tw (bits 5 and 1 in ) Tj
71.04 0 TD /F0 12 Tf
0.0133 Tc 0 Tw (IN_STATUS) Tj
66 0 TD /F1 12 Tf
0 Tc (.) Tj
287.04 27.84 TD (0) Tj
-424.08 -49.92 TD /F0 12 Tf
-0.0343 Tc 0.1543 Tw (not used) Tj
424.08 0 TD /F1 12 Tf
0 Tc 0 Tw (1) Tj
-424.08 -22.08 TD /F0 12 Tf
-0.015 Tc (OUT_LEDS) Tj
63.36 0 TD /F1 12 Tf
0.0261 Tc -0.1461 Tw (: Turns each of the 8 LEDs on or off. 1 turns LED on.\(Avnet ) Tj
-63.36 -13.92 TD 0.1029 Tc -0.3429 Tw (board specific\)) Tj
424.08 13.92 TD 0 Tc 0 Tw (2) Tj
ET
71.76 100.32 0.48 419.52 re f
453.36 99.84 0.48 420.48 re f
495.84 99.84 0.48 420.48 re f
537.12 100.32 0.48 419.52 re f
71.76 520.32 m
71.76 519.84 l
537.6 519.84 l
537.6 520.32 l
h
f
72.24 495.6 m
72.24 495.12 l
537.12 495.12 l
537.12 495.6 l
h
f
72.24 492.96 m
72.24 492.48 l
537.12 492.48 l
537.12 492.96 l
h
f
71.76 444.24 m
71.76 443.76 l
537.6 443.76 l
537.6 444.24 l
h
f
71.76 310.32 m
71.76 309.84 l
537.6 309.84 l
537.6 310.32 l
h
f
71.76 274.32 m
71.76 273.84 l
537.6 273.84 l
537.6 274.32 l
h
f
71.76 252.24 m
71.76 251.76 l
537.6 251.76 l
537.6 252.24 l
h
f
71.76 230.16 m
71.76 229.68 l
537.6 229.68 l
537.6 230.16 l
h
f
71.76 208.32 m
71.76 207.84 l
537.6 207.84 l
537.6 208.32 l
h
f
71.76 158.16 m
71.76 157.68 l
537.6 157.68 l
537.6 158.16 l
h
f
71.76 136.32 m
71.76 135.84 l
537.6 135.84 l
537.6 136.32 l
h
f
71.76 100.32 m
71.76 99.84 l
537.6 99.84 l
537.6 100.32 l
h
f
endstream
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5365
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27 0 obj
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BT
77.76 502.08 TD
0 0 0 rg
/F1 12 Tf
0.0554 Tc 0.0779 Tw (The I/O ports are not in the focus of this document, so please refer to the VHDL files regarding) Tj
-5.76 -14.16 TD 0.0829 Tc 0.1571 Tw (theit implementation. You may find the baudrate generator interesting due to its unlimited preci-) Tj
0 -13.92 TD 0.064 Tc -0.204 Tw (sion, and the Rx and Tx parts due to their very low size.) Tj
0 -29.28 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (4.5) Tj
56.64 0 TD 0.0141 Tc (cpu_engine.vhd) Tj
-50.88 -18.72 TD /F1 12 Tf
0.06 Tc -0.14 Tw (This is the CPU itself. The structure of the ) Tj
206.4 0 TD /F0 12 Tf
-0.024 Tc 0 Tw (cpu_engine) Tj
58.08 0 TD /F1 12 Tf
0.14 Tc -0.3 Tw ( is as follows:) Tj
-264.48 -244.08 TD 0.0512 Tc 0.9088 Tw (The memory signals are also extended to the outside of this module in order to connect to an) Tj
-5.76 -13.92 TD 0.0429 Tc -0.1229 Tw (optional external SRAM and to the ) Tj
171.12 0 TD /F0 12 Tf
-0.015 Tc 0 Tw (input_output.vhd) Tj
89.76 0 TD /F1 12 Tf
0.1029 Tc -0.3429 Tw ( module.) Tj
-255.12 -19.92 TD 0.3105 Tw (The timing is as follows. All signals are clocked on the rising edge of the 40 MHz input clock.) Tj
-5.76 -14.16 TD 0.0759 Tc 0.2241 Tw (However, most signals are clocked on every second clock only. This is controlled by the T2 sig-) Tj
0 -13.92 TD 0.0896 Tc -0.0736 Tw (nal. The internal memory is dual-ported, but only to save address and data multiplexers. The first) Tj
T* 0.0429 Tc -0.2429 Tw (clock interval \(say T1, or better ) Tj
-2.64 Tc 0 Tw (\221) Tj
-0.096 Tc -0.144 Tw (not T2) Tj
-2.64 Tc 0 Tw (\222) Tj
0.0511 Tc -0.2474 Tw (\) is used for opcode reads, while the second phase \(T2\) is) Tj
0 -14.16 TD 0.0356 Tc -0.1556 Tw (used for all other \(that is, oprand transfers; immediate operands are counted as opcode reads\).) Tj
6 588 TD /F0 12 Tf
0.02 Tc 0 Tw (OUT_INT_MASK) Tj
95.28 0 TD /F1 12 Tf
0.0587 Tc -0.2114 Tw (: The interrupt maks for Rx, Tx and Timer interrupts. 1 ) Tj
-95.28 -13.92 TD 0.1 Tc -0.18 Tw (means interrupt is enabled.) Tj
0 -13.92 TD 0 Tc -0.16 Tw (Bit 7..3: not used) Tj
0 -14.16 TD 0.0821 Tc -0.1621 Tw (Bit 2:Enable Timer interrupt \(1 ms interval\)) Tj
0 -13.92 TD 0.0785 Tc -0.2385 Tw (Bit 1: Enable Rx Interrupt \(receiver has received valid data\)) Tj
T* 0.0185 Tc -0.1785 Tw (Bit 0: Enable Tx Interrupt \(transmitter ready to accept data\)) Tj
424.08 69.84 TD 0 Tc 0 Tw (3) Tj
-424.08 -91.92 TD /F0 12 Tf
-0.024 Tc (OUT_RESET_TIMER) Tj
117.84 0 TD /F1 12 Tf
0.0857 Tc -0.1457 Tw (: Writing clears Timer interrupt) Tj
306.24 0 TD 0 Tc 0 Tw (4) Tj
-424.08 -22.08 TD /F0 12 Tf
-0.0141 Tc (OUT_START_CLK_CTR) Tj
135.36 0 TD /F1 12 Tf
-0.0065 Tc -0.1135 Tw (: Start a 16 bit counter clocked at a rate of 20 ) Tj
-135.36 -13.92 TD 0.1111 Tc -0.2611 Tw (MHz. Useful for measuring short intervals with high precision.) Tj
424.08 13.92 TD 0 Tc 0 Tw (5) Tj
-424.08 -36 TD /F0 12 Tf
-0.0075 Tc (OUT_STOP_CLK_CTR) Tj
126.72 0 TD /F1 12 Tf
-0.024 Tc -0.072 Tw (: Stop the 16 bit counter) Tj
25.2 174 TD -0.04 Tc 0.04 Tw (Port Function) Tj
238.56 0 TD -0.12 Tc 0 Tw (IN) Tj
36 0 TD 0 Tc (OUT) Tj
ET
71.76 522.24 0.48 197.52 re f
453.36 521.76 0.48 198.48 re f
495.84 521.76 0.48 198.48 re f
537.12 522.24 0.48 197.52 re f
71.76 720.24 m
71.76 719.76 l
537.6 719.76 l
537.6 720.24 l
h
f
72.24 695.52 m
72.24 695.04 l
537.12 695.04 l
537.12 695.52 l
h
f
72.24 693.12 m
72.24 692.64 l
537.12 692.64 l
537.12 693.12 l
h
f
71.76 602.16 m
71.76 601.68 l
537.6 601.68 l
537.6 602.16 l
h
f
71.76 580.32 m
71.76 579.84 l
537.6 579.84 l
537.6 580.32 l
h
f
71.76 544.32 m
71.76 543.84 l
537.6 543.84 l
537.6 544.32 l
h
f
71.76 522.24 m
71.76 521.76 l
537.6 521.76 l
537.6 522.24 l
h
f
1 1 1 rg
72 217.92 468 184.08 re f
444.72 239.04 84.96 42.48 re f
0 0 0 rg
444.72 279.84 86.64 3.12 re f
528.24 237.36 3.12 44.16 re f
443.28 237.36 86.4 3.12 re f
443.28 239.04 3.12 43.92 re f
BT
462 254.88 TD
/F0 12 Tf
0.0133 Tc (data_core) Tj
ET
1 1 1 rg
260.4 239.04 85.2 42.48 re f
0 0 0 rg
260.4 279.84 86.88 3.12 re f
344.16 237.36 3.12 44.16 re f
258.96 237.36 86.64 3.12 re f
258.96 239.04 3.12 43.92 re f
BT
281.76 254.88 TD
0.08 Tc (memory) Tj
ET
1 1 1 rg
76.32 239.04 84.96 42.48 re f
0 0 0 rg
76.32 279.84 86.64 3.12 re f
159.84 237.36 3.12 44.16 re f
74.88 237.36 86.4 3.12 re f
74.88 239.04 3.12 43.92 re f
BT
85.2 254.88 TD
0.01 Tc (opcode_fetch) Tj
ET
1 1 1 rg
253.44 338.16 99.12 42.48 re f
0 0 0 rg
253.44 378.96 100.8 3.12 re f
351.12 336.48 3.12 44.16 re f
252 336.48 100.56 3.12 re f
252 338.16 3.12 43.92 re f
BT
261.6 354.24 TD
-0.0171 Tc (opcode_decoder) Tj
ET
248.88 260.16 m
248.88 263.52 l
249.6 263.28 l
258.96 260.64 l
260.64 260.16 l
258.96 259.68 l
249.6 257.04 l
248.88 256.8 l
248.88 257.52 l
249.36 258 l
258.72 260.64 l
258.96 259.68 l
258.72 259.68 l
249.36 262.32 l
249.6 263.28 l
249.84 262.8 l
249.84 260.16 l
h
f
248.88 257.52 m
248.88 260.16 l
249.84 260.16 l
249.84 257.52 l
h
f
249.36 260.16 m
249.36 262.8 l
258.72 260.16 l
249.36 257.52 l
h
f*
161.04 259.92 0.24 0.48 re f
248.88 259.92 0.24 0.48 re f
161.28 260.4 m
161.28 259.92 l
248.88 259.92 l
248.88 260.4 l
h
f
357.12 274.32 m
357.12 270.96 l
356.4 271.2 l
347.04 273.84 l
345.36 274.32 l
347.04 274.8 l
356.4 277.68 l
357.12 277.92 l
357.12 277.2 l
356.64 276.72 l
347.28 273.84 l
347.04 274.8 l
347.28 274.8 l
356.64 272.16 l
356.4 271.2 l
356.16 271.68 l
356.16 274.32 l
h
f
357.12 277.2 m
357.12 274.32 l
356.16 274.32 l
356.16 277.2 l
h
f
356.64 274.32 m
356.64 271.68 l
347.28 274.32 l
356.64 277.2 l
h
f*
356.88 274.08 0.24 0.48 re f
444.72 274.08 0.24 0.48 re f
357.12 274.56 m
357.12 274.08 l
444.72 274.08 l
444.72 274.56 l
h
f
274.56 326.64 m
271.2 326.64 l
271.44 327.36 l
274.08 336.72 l
274.56 338.4 l
275.04 336.72 l
277.68 327.36 l
277.92 326.64 l
277.2 326.64 l
276.72 327.12 l
274.08 336.48 l
275.04 336.72 l
275.04 336.48 l
272.4 327.12 l
271.44 327.36 l
271.92 327.6 l
274.56 327.6 l
h
f
277.2 326.64 m
274.56 326.64 l
274.56 327.6 l
277.2 327.6 l
h
f
274.56 327.12 m
271.92 327.12 l
274.56 336.48 l
277.2 327.12 l
h
f*
274.32 281.52 m
274.32 281.28 l
274.8 281.28 l
274.8 281.52 l
h
f
274.32 326.64 m
274.32 326.88 l
274.8 326.88 l
274.8 326.64 l
h
f
274.32 281.52 0.48 45.12 re f
357.12 260.16 m
357.12 256.8 l
356.4 257.04 l
347.04 259.68 l
345.36 260.16 l
347.04 260.64 l
356.4 263.28 l
357.12 263.52 l
357.12 262.8 l
356.64 262.32 l
347.28 259.68 l
347.04 260.64 l
347.28 260.64 l
356.64 258 l
356.4 257.04 l
356.16 257.52 l
356.16 260.16 l
h
f
357.12 262.8 m
357.12 260.16 l
356.16 260.16 l
356.16 262.8 l
h
f
356.64 260.16 m
356.64 257.52 l
347.28 260.16 l
356.64 262.8 l
h
f*
356.88 259.92 0.24 0.48 re f
444.72 259.92 0.24 0.48 re f
357.12 260.4 m
357.12 259.92 l
444.72 259.92 l
444.72 260.4 l
h
f
BT
175.44 262.32 TD
/F0 9.84 Tf
0.1056 Tc (PC) Tj
106.56 45.84 TD 0.152 Tc (OPC) Tj
ET
487.2 293.04 m
490.56 293.04 l
490.32 292.32 l
487.68 283.2 l
487.2 281.52 l
486.72 283.2 l
484.08 292.32 l
483.84 293.04 l
484.56 293.04 l
485.04 292.56 l
487.68 283.44 l
486.72 283.2 l
486.72 283.44 l
489.36 292.56 l
490.32 292.32 l
489.84 292.08 l
487.2 292.08 l
h
f
484.56 293.04 m
487.2 293.04 l
487.2 292.08 l
484.56 292.08 l
h
f
487.2 292.56 m
489.84 292.56 l
487.2 283.44 l
484.56 292.56 l
h
f*
352.32 359.28 0.24 0.48 re f
356.4 359.28 0.24 0.48 re f
352.56 359.76 m
352.56 359.28 l
356.4 359.28 l
356.4 359.76 l
h
f
362.4 359.28 0.24 0.48 re f*
369.84 359.28 0.24 0.48 re f*
362.64 359.76 m
362.64 359.28 l
369.84 359.28 l
369.84 359.76 l
h
f*
375.84 359.28 0.24 0.48 re f*
383.28 359.28 0.24 0.48 re f*
376.08 359.76 m
376.08 359.28 l
383.28 359.28 l
383.28 359.76 l
h
f*
389.28 359.28 0.24 0.48 re f*
396.72 359.28 0.24 0.48 re f*
389.52 359.76 m
389.52 359.28 l
396.72 359.28 l
396.72 359.76 l
h
f*
402.72 359.28 0.24 0.48 re f*
410.16 359.28 0.24 0.48 re f*
402.96 359.76 m
402.96 359.28 l
410.16 359.28 l
410.16 359.76 l
h
f*
416.16 359.28 0.24 0.48 re f*
423.6 359.28 0.24 0.48 re f*
416.4 359.76 m
416.4 359.28 l
423.6 359.28 l
423.6 359.76 l
h
f*
429.6 359.28 0.24 0.48 re f*
437.04 359.28 0.24 0.48 re f*
429.84 359.76 m
429.84 359.28 l
437.04 359.28 l
437.04 359.76 l
h
f*
443.04 359.28 0.24 0.48 re f*
450.48 359.28 0.24 0.48 re f*
443.28 359.76 m
443.28 359.28 l
450.48 359.28 l
450.48 359.76 l
h
f*
456.48 359.28 0.24 0.48 re f*
463.92 359.28 0.24 0.48 re f*
456.72 359.76 m
456.72 359.28 l
463.92 359.28 l
463.92 359.76 l
h
f*
469.92 359.28 0.24 0.48 re f*
477.36 359.28 0.24 0.48 re f*
470.16 359.76 m
470.16 359.28 l
477.36 359.28 l
477.36 359.76 l
h
f*
483.36 359.28 0.24 0.48 re f
483.6 359.28 3.84 0.48 re f
487.44 355.68 m
487.44 355.44 l
486.96 355.44 l
486.96 355.68 l
h
f
486.96 355.68 0.48 3.84 re f
487.44 349.68 m
487.44 349.92 l
486.96 349.92 l
486.96 349.68 l
h
f*
487.44 342.48 m
487.44 342.24 l
486.96 342.24 l
486.96 342.48 l
h
f*
486.96 342.48 0.48 7.2 re f*
487.44 336.48 m
487.44 336.72 l
486.96 336.72 l
486.96 336.48 l
h
f*
487.44 329.28 m
487.44 329.04 l
486.96 329.04 l
486.96 329.28 l
h
f*
486.96 329.28 0.48 7.2 re f*
487.44 323.28 m
487.44 323.52 l
486.96 323.52 l
486.96 323.28 l
h
f*
487.44 316.08 m
487.44 315.84 l
486.96 315.84 l
486.96 316.08 l
h
f*
486.96 316.08 0.48 7.2 re f*
487.44 310.08 m
487.44 310.32 l
486.96 310.32 l
486.96 310.08 l
h
f*
487.44 302.88 m
487.44 302.64 l
486.96 302.64 l
486.96 302.88 l
h
f*
486.96 302.88 0.48 7.2 re f*
487.44 296.88 m
487.44 297.12 l
486.96 297.12 l
486.96 296.88 l
h
f
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487.44 292.8 l
486.96 292.8 l
486.96 293.04 l
h
f
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122.16 293.04 l
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119.28 283.2 l
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115.68 292.32 l
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116.64 292.56 l
119.28 283.44 l
118.32 283.2 l
118.32 283.44 l
120.96 292.56 l
121.92 292.32 l
121.44 292.08 l
118.8 292.08 l
h
f
116.16 293.04 m
118.8 293.04 l
118.8 292.08 l
116.16 292.08 l
h
f
118.8 292.56 m
121.44 292.56 l
118.8 283.44 l
116.16 292.56 l
h
f*
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249.36 352.08 0.24 0.48 re f
253.44 352.08 m
253.44 352.56 l
249.6 352.56 l
249.6 352.08 l
h
f
243.36 352.08 0.24 0.48 re f*
235.92 352.08 0.24 0.48 re f*
243.36 352.08 m
243.36 352.56 l
236.16 352.56 l
236.16 352.08 l
h
f*
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222.48 352.08 0.24 0.48 re f*
229.92 352.08 m
229.92 352.56 l
222.72 352.56 l
222.72 352.08 l
h
f*
216.48 352.08 0.24 0.48 re f*
209.04 352.08 0.24 0.48 re f*
216.48 352.08 m
216.48 352.56 l
209.28 352.56 l
209.28 352.08 l
h
f*
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195.6 352.08 0.24 0.48 re f*
203.04 352.08 m
203.04 352.56 l
195.84 352.56 l
195.84 352.08 l
h
f*
189.6 352.08 0.24 0.48 re f*
182.16 352.08 0.24 0.48 re f*
189.6 352.08 m
189.6 352.56 l
182.4 352.56 l
182.4 352.08 l
h
f*
176.16 352.08 0.24 0.48 re f*
168.72 352.08 0.24 0.48 re f*
176.16 352.08 m
176.16 352.56 l
168.96 352.56 l
168.96 352.08 l
h
f*
162.72 352.08 0.24 0.48 re f*
155.28 352.08 0.24 0.48 re f*
162.72 352.08 m
162.72 352.56 l
155.52 352.56 l
155.52 352.08 l
h
f*
149.28 352.08 0.24 0.48 re f*
141.84 352.08 0.24 0.48 re f*
149.28 352.08 m
149.28 352.56 l
142.08 352.56 l
142.08 352.08 l
h
f*
135.84 352.08 0.24 0.48 re f*
128.4 352.08 0.24 0.48 re f*
135.84 352.08 m
135.84 352.56 l
128.64 352.56 l
128.64 352.08 l
h
f*
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118.56 352.08 3.84 0.48 re f
119.04 348.72 m
119.04 348.48 l
118.56 348.48 l
118.56 348.72 l
h
f
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119.04 341.76 m
119.04 342 l
118.56 342 l
118.56 341.76 l
h
f*
119.04 333.6 m
119.04 333.36 l
118.56 333.36 l
118.56 333.6 l
h
f*
118.56 333.6 0.48 8.16 re f*
119.04 326.64 m
119.04 326.88 l
118.56 326.88 l
118.56 326.64 l
h
f*
119.04 318.72 m
119.04 318.48 l
118.56 318.48 l
118.56 318.72 l
h
f*
118.56 318.72 0.48 7.92 re f*
119.04 311.76 m
119.04 312 l
118.56 312 l
118.56 311.76 l
h
f*
119.04 303.84 m
119.04 303.6 l
118.56 303.6 l
118.56 303.84 l
h
f*
118.56 303.84 0.48 7.92 re f*
119.04 296.88 m
119.04 297.12 l
118.56 297.12 l
118.56 296.88 l
h
f
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119.04 292.8 l
118.56 292.8 l
118.56 293.04 l
h
f
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327.6 293.04 l
327.36 292.32 l
324.72 283.2 l
324.24 281.52 l
323.76 283.2 l
321.12 292.32 l
320.88 293.04 l
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322.08 292.56 l
324.72 283.44 l
323.76 283.2 l
323.76 283.44 l
326.4 292.56 l
327.36 292.32 l
326.88 292.08 l
324.24 292.08 l
h
f
321.6 293.04 m
324.24 293.04 l
324.24 292.08 l
321.6 292.08 l
h
f
324.24 292.56 m
326.88 292.56 l
324.24 283.44 l
321.6 292.56 l
h
f*
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324.48 338.4 l
324 338.4 l
324 338.16 l
h
f
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324.48 334.32 l
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324 334.56 l
h
f
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324.48 327.36 m
324.48 327.6 l
324 327.6 l
324 327.36 l
h
f*
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324.48 318.96 l
324 318.96 l
324 319.2 l
h
f*
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324.48 312.24 l
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h
f*
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324.48 303.6 l
324 303.6 l
324 303.84 l
h
f*
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324.48 297.12 l
324 297.12 l
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h
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h
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ET
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h
f
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433.2 246 l
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434.16 243.36 l
h
f
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433.68 248.64 l
442.8 246 l
433.68 243.36 l
h
f*
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345.6 245.76 l
433.2 245.76 l
433.2 246.24 l
h
f
BT
388.08 262.32 TD
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251.52 373.2 l
239.52 376.56 l
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h
f
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239.04 373.68 l
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240 370.08 l
h
f
239.52 373.68 m
239.52 377.04 l
251.52 373.68 l
239.52 370.08 l
h
f*
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239.04 373.2 0.48 0.96 re f
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217.92 373.2 l
239.04 373.2 l
239.04 374.16 l
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BT
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0.0554 Tc 0.0779 Tw (The I/O ports are not in the focus of this document, so please refer to the VHDL files regarding) Tj
-5.76 -14.16 TD 0.0829 Tc 0.1571 Tw (theit implementation. You may find the baudrate generator interesting due to its unlimited preci-) Tj
0 -13.92 TD 0.064 Tc -0.204 Tw (sion, and the Rx and Tx parts due to their very low size.) Tj
0 -29.28 TD /F0 13.92 Tf
-0.04 Tc 0 Tw (4.5) Tj
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-50.88 -18.72 TD /F1 12 Tf
0.06 Tc -0.14 Tw (This is the CPU itself. The structure of the ) Tj
206.4 0 TD /F0 12 Tf
-0.024 Tc 0 Tw (cpu_engine) Tj
58.08 0 TD /F1 12 Tf
0.14 Tc -0.3 Tw ( is as follows:) Tj
-264.48 -244.08 TD 0.0512 Tc 0.9088 Tw (The memory signals are also extended to the outside of this module in order to connect to an) Tj
-5.76 -13.92 TD 0.0429 Tc -0.1229 Tw (optional external SRAM and to the ) Tj
171.12 0 TD /F0 12 Tf
-0.015 Tc 0 Tw (input_output.vhd) Tj
89.76 0 TD /F1 12 Tf
0.1029 Tc -0.3429 Tw ( module.) Tj
-255.12 -19.92 TD 0.3105 Tw (The timing is as follows. All signals are clocked on the rising edge of the 40 MHz input clock.) Tj
-5.76 -14.16 TD 0.0759 Tc 0.2241 Tw (However, most signals are clocked on every second clock only. This is controlled by the T2 sig-) Tj
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-2.64 Tc 0 Tw (\221) Tj
-0.096 Tc -0.144 Tw (not T2) Tj
-2.64 Tc 0 Tw (\222) Tj
0.0511 Tc -0.2474 Tw (\) is used for opcode reads, while the second phase \(T2\) is) Tj
0 -14.16 TD 0.0356 Tc -0.1556 Tw (used for all other \(that is, oprand transfers; immediate operands are counted as opcode reads\).) Tj
6 588 TD /F0 12 Tf
0.02 Tc 0 Tw (OUT_INT_MASK) Tj
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0.0587 Tc -0.2114 Tw (: The interrupt maks for Rx, Tx and Timer interrupts. 1 ) Tj
-95.28 -13.92 TD 0.1 Tc -0.18 Tw (means interrupt is enabled.) Tj
0 -13.92 TD 0 Tc -0.16 Tw (Bit 7..3: not used) Tj
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0 -13.92 TD 0.0785 Tc -0.2385 Tw (Bit 1: Enable Rx Interrupt \(receiver has received valid data\)) Tj
T* 0.0185 Tc -0.1785 Tw (Bit 0: Enable Tx Interrupt \(transmitter ready to accept data\)) Tj
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-0.024 Tc (OUT_RESET_TIMER) Tj
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0.0857 Tc -0.1457 Tw (: Writing clears Timer interrupt) Tj
306.24 0 TD 0 Tc 0 Tw (4) Tj
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-0.0065 Tc -0.1135 Tw (: Start a 16 bit counter clocked at a rate of 20 ) Tj
-135.36 -13.92 TD 0.1111 Tc -0.2611 Tw (MHz. Useful for measuring short intervals with high precision.) Tj
424.08 13.92 TD 0 Tc 0 Tw (5) Tj
-424.08 -36 TD /F0 12 Tf
-0.0075 Tc (OUT_STOP_CLK_CTR) Tj
126.72 0 TD /F1 12 Tf
-0.024 Tc -0.072 Tw (: Stop the 16 bit counter) Tj
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36 0 TD 0 Tc (OUT) Tj
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71.76 719.76 l
537.6 719.76 l
537.6 720.24 l
h
f
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72.24 695.04 l
537.12 695.04 l
537.12 695.52 l
h
f
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72.24 692.64 l
537.12 692.64 l
537.12 693.12 l
h
f
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537.6 602.16 l
h
f
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537.6 580.32 l
h
f
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h
f
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71.76 521.76 l
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161.28 259.92 l
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h
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356.64 271.68 l
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356.64 277.2 l
h
f*
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357.12 274.08 l
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271.44 327.36 l
271.92 327.6 l
274.56 327.6 l
h
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274.56 326.64 l
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277.2 327.6 l
h
f
274.56 327.12 m
271.92 327.12 l
274.56 336.48 l
277.2 327.12 l
h
f*
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274.32 281.28 l
274.8 281.28 l
274.8 281.52 l
h
f
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274.32 326.88 l
274.8 326.88 l
274.8 326.64 l
h
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347.04 259.68 l
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347.28 260.64 l
356.64 258 l
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356.16 257.52 l
356.16 260.16 l
h
f
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357.12 260.16 l
356.16 260.16 l
356.16 262.8 l
h
f
356.64 260.16 m
356.64 257.52 l
347.28 260.16 l
356.64 262.8 l
h
f*
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357.12 260.4 m
357.12 259.92 l
444.72 259.92 l
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490.56 293.04 l
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484.56 293.04 l
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486.72 283.44 l
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487.2 292.08 l
h
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487.2 293.04 l
487.2 292.08 l
484.56 292.08 l
h
f
487.2 292.56 m
489.84 292.56 l
487.2 283.44 l
484.56 292.56 l
h
f*
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356.4 359.28 0.24 0.48 re f
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352.56 359.28 l
356.4 359.28 l
356.4 359.76 l
h
f
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369.84 359.28 0.24 0.48 re f*
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362.64 359.28 l
369.84 359.28 l
369.84 359.76 l
h
f*
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376.08 359.28 l
383.28 359.28 l
383.28 359.76 l
h
f*
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389.52 359.28 l
396.72 359.28 l
396.72 359.76 l
h
f*
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402.96 359.28 l
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410.16 359.76 l
h
f*
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416.4 359.28 l
423.6 359.28 l
423.6 359.76 l
h
f*
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429.84 359.28 l
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437.04 359.76 l
h
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443.28 359.28 l
450.48 359.28 l
450.48 359.76 l
h
f*
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463.92 359.28 0.24 0.48 re f*
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456.72 359.28 l
463.92 359.28 l
463.92 359.76 l
h
f*
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477.36 359.28 0.24 0.48 re f*
470.16 359.76 m
470.16 359.28 l
477.36 359.28 l
477.36 359.76 l
h
f*
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483.6 359.28 3.84 0.48 re f
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487.44 355.44 l
486.96 355.44 l
486.96 355.68 l
h
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487.44 349.68 m
487.44 349.92 l
486.96 349.92 l
486.96 349.68 l
h
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487.44 342.24 l
486.96 342.24 l
486.96 342.48 l
h
f*
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487.44 336.48 m
487.44 336.72 l
486.96 336.72 l
486.96 336.48 l
h
f*
487.44 329.28 m
487.44 329.04 l
486.96 329.04 l
486.96 329.28 l
h
f*
486.96 329.28 0.48 7.2 re f*
487.44 323.28 m
487.44 323.52 l
486.96 323.52 l
486.96 323.28 l
h
f*
487.44 316.08 m
487.44 315.84 l
486.96 315.84 l
486.96 316.08 l
h
f*
486.96 316.08 0.48 7.2 re f*
487.44 310.08 m
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