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186.24 708 TD
0 0 0 rg
/F0 18 Tf
0.0346 Tc -0.0766 Tw (Instruction Set of the C16 CPU) Tj
-114.24 -61.44 TD /F0 13.92 Tf
0.0966 Tc 0 Tw (Abbreviations) Tj
0 -20.64 TD /F1 12 Tf
0 Tc (UL) Tj
56.64 0 TD 0.0828 Tc -0.2028 Tw (low byte of 16 bit unsigned operand) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (UH) Tj
56.64 0 TD 0.104 Tc -0.224 Tw (high byte of 16 bit unsigned operand) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (U8) Tj
56.64 0 TD 0.0695 Tc -0.138 Tw (8 bit unsigned operand, will be zero extended) Tj
-56.64 -14.16 TD 0 Tc 0 Tw (U4) Tj
56.64 0 TD 0.0655 Tc -0.1615 Tw (4 bit unsigned operand contained in opcode, will be zero extended) Tj
-56.64 -27.84 TD 0 Tc 0 Tw (SL) Tj
56.64 0 TD 0.08 Tc -0.2 Tw (low byte of 16 bit signed operand) Tj
-56.64 -14.16 TD 0 Tc 0 Tw (SH) Tj
56.64 0 TD 0.1029 Tc -0.2229 Tw (high byte of 16 bit signed operand) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (S8) Tj
56.64 0 TD 0.1232 Tc -0.3232 Tw (8 bitnsigned operand, will be sign extended) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (S4) Tj
56.64 0 TD 0.086 Tc -0.182 Tw (4 bit signed operand contained in opcode, will be sign extended) Tj
-56.64 -28.08 TD 0 Tc 0 Tw (u) Tj
56.64 0 TD 0.08 Tc -0.1333 Tw (an unsigned immediate operand \(zero extended if < 16 bit\)) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (s) Tj
56.64 0 TD 0.1013 Tc -0.1813 Tw (a signed immediate operand \(sign extended if < 16 bit\)) Tj
-56.64 -14.16 TD 0 Tc 0 Tw (uRR) Tj
56.64 0 TD 0.1248 Tc -0.3648 Tw (RR unsigned \(in comparisons\)) Tj
-56.64 -13.92 TD 0.08 Tc 0 Tw (sRR) Tj
56.64 0 TD 0.1252 Tc -0.3652 Tw (RR signed \(in comparisons\)) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (RU) Tj
56.64 0 TD 0.0514 Tc -0.1514 Tw (RR, but the 8 bit operand is zero extended. Implies 8 buit transfer.) Tj
-56.64 -14.16 TD 0 Tc 0 Tw (RS) Tj
56.64 0 TD 0.0729 Tc -0.1729 Tw (RR, but the 8 bit operand is sign extended. Implies 8 buit transfer.) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (R) Tj
56.64 0 TD 0.1018 Tc -0.239 Tw (low byte of RR. Implies 8 buit transfer.) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (uLL) Tj
56.64 0 TD 0.096 Tc -0.096 Tw (LL unsigned \(in comparisons\)) Tj
-56.64 -14.16 TD 0.08 Tc 0 Tw (sLL) Tj
56.64 0 TD 0.0939 Tc -0.0939 Tw (LL signed \(in comparisons\)) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (LU) Tj
56.64 0 TD 0.0643 Tc -0.2043 Tw (LL, but the 8 bit operand is zero extended. Implies 8 buit transfer.) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (LS) Tj
56.64 0 TD 0.0857 Tc -0.2457 Tw (LL, but the 8 bit operand is sign extended. Implies 8 buit transfer.) Tj
-56.64 -14.16 TD 0 Tc 0 Tw (L) Tj
56.64 0 TD 0.1164 Tc -0.3221 Tw (low byte of LL. Implies 8 buit transfer.) Tj
-56.64 -13.92 TD 0.24 Tc 0 Tw (iff) Tj
56.64 0 TD -0.4 Tw (if and only if) Tj
-56.64 -28.08 TD 0.039 Tc -0.189 Tw (Some opcodes exist in a quick, short, or long format. The assembler generates the proper opcode ) Tj
0 -13.92 TD 0.0579 Tc -0.2019 Tw (based on the actual operand value.) Tj
0 -29.28 TD /F0 13.92 Tf
0.082 Tc -0.1237 Tw (Opcodes of the S16 CPU) Tj
30.48 -52.8 TD /F0 12 Tf
0.0276 Tc 0.0564 Tw (Opcode Byte) Tj
109.92 -12.96 TD 0.0192 Tc 0.0648 Tw (Assembler Syntax) Tj
190.08 0 TD 0.048 Tc 0 Tw (Operation) Tj
-312.72 -12.96 TD /F1 12 Tf
0 Tc (1) Tj
41.76 0 TD (2) Tj
42.72 0 TD (3) Tj
-96.24 -24 TD (00) Tj
126.48 0 TD 0.06 Tc (HALT) Tj
120.48 0 TD 0.1018 Tc -0.2458 Tw (HALT until next interrupt \(if enabled\)) Tj
-246.96 -22.08 TD 0 Tc 0 Tw (01) Tj
126.48 0 TD (NOP) Tj
120.48 0 TD 0.0533 Tc -0.2933 Tw (Do nothing) Tj
-246.96 -21.84 TD 0 Tc 0 Tw (02) Tj
126.48 0 TD -0.12 Tw (JMP u) Tj
120.48 0 TD (PC := u) Tj
ET
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113.04 91.68 0.48 92.64 re f
155.76 91.68 0.48 92.64 re f
198.24 91.68 0.48 118.56 re f
318.72 91.68 0.48 118.56 re f
538.32 92.16 0.48 117.6 re f
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71.76 209.76 l
538.8 209.76 l
538.8 210.24 l
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71.76 184.32 m
71.76 183.84 l
198.72 183.84 l
198.72 184.32 l
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72.24 159.6 m
72.24 159.12 l
538.32 159.12 l
538.32 159.6 l
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72.24 156.48 l
538.32 156.48 l
538.32 156.96 l
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71.76 136.32 m
71.76 135.84 l
538.8 135.84 l
538.8 136.32 l
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71.76 114.24 m
71.76 113.76 l
538.8 113.76 l
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71.76 92.16 m
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186.24 708 TD
0 0 0 rg
/F0 18 Tf
0.0346 Tc -0.0766 Tw (Instruction Set of the C16 CPU) Tj
-114.24 -61.44 TD /F0 13.92 Tf
0.0966 Tc 0 Tw (Abbreviations) Tj
0 -20.64 TD /F1 12 Tf
0 Tc (UL) Tj
56.64 0 TD 0.0828 Tc -0.2028 Tw (low byte of 16 bit unsigned operand) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (UH) Tj
56.64 0 TD 0.104 Tc -0.224 Tw (high byte of 16 bit unsigned operand) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (U8) Tj
56.64 0 TD 0.0695 Tc -0.138 Tw (8 bit unsigned operand, will be zero extended) Tj
-56.64 -14.16 TD 0 Tc 0 Tw (U4) Tj
56.64 0 TD 0.0655 Tc -0.1615 Tw (4 bit unsigned operand contained in opcode, will be zero extended) Tj
-56.64 -27.84 TD 0 Tc 0 Tw (SL) Tj
56.64 0 TD 0.08 Tc -0.2 Tw (low byte of 16 bit signed operand) Tj
-56.64 -14.16 TD 0 Tc 0 Tw (SH) Tj
56.64 0 TD 0.1029 Tc -0.2229 Tw (high byte of 16 bit signed operand) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (S8) Tj
56.64 0 TD 0.1232 Tc -0.3232 Tw (8 bitnsigned operand, will be sign extended) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (S4) Tj
56.64 0 TD 0.086 Tc -0.182 Tw (4 bit signed operand contained in opcode, will be sign extended) Tj
-56.64 -28.08 TD 0 Tc 0 Tw (u) Tj
56.64 0 TD 0.08 Tc -0.1333 Tw (an unsigned immediate operand \(zero extended if < 16 bit\)) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (s) Tj
56.64 0 TD 0.1013 Tc -0.1813 Tw (a signed immediate operand \(sign extended if < 16 bit\)) Tj
-56.64 -14.16 TD 0 Tc 0 Tw (uRR) Tj
56.64 0 TD 0.1248 Tc -0.3648 Tw (RR unsigned \(in comparisons\)) Tj
-56.64 -13.92 TD 0.08 Tc 0 Tw (sRR) Tj
56.64 0 TD 0.1252 Tc -0.3652 Tw (RR signed \(in comparisons\)) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (RU) Tj
56.64 0 TD 0.0514 Tc -0.1514 Tw (RR, but the 8 bit operand is zero extended. Implies 8 buit transfer.) Tj
-56.64 -14.16 TD 0 Tc 0 Tw (RS) Tj
56.64 0 TD 0.0729 Tc -0.1729 Tw (RR, but the 8 bit operand is sign extended. Implies 8 buit transfer.) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (R) Tj
56.64 0 TD 0.1018 Tc -0.239 Tw (low byte of RR. Implies 8 buit transfer.) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (uLL) Tj
56.64 0 TD 0.096 Tc -0.096 Tw (LL unsigned \(in comparisons\)) Tj
-56.64 -14.16 TD 0.08 Tc 0 Tw (sLL) Tj
56.64 0 TD 0.0939 Tc -0.0939 Tw (LL signed \(in comparisons\)) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (LU) Tj
56.64 0 TD 0.0643 Tc -0.2043 Tw (LL, but the 8 bit operand is zero extended. Implies 8 buit transfer.) Tj
-56.64 -13.92 TD 0 Tc 0 Tw (LS) Tj
56.64 0 TD 0.0857 Tc -0.2457 Tw (LL, but the 8 bit operand is sign extended. Implies 8 buit transfer.) Tj
-56.64 -14.16 TD 0 Tc 0 Tw (L) Tj
56.64 0 TD 0.1164 Tc -0.3221 Tw (low byte of LL. Implies 8 buit transfer.) Tj
-56.64 -13.92 TD 0.24 Tc 0 Tw (iff) Tj
56.64 0 TD -0.4 Tw (if and only if) Tj
-56.64 -28.08 TD 0.039 Tc -0.189 Tw (Some opcodes exist in a quick, short, or long format. The assembler generates the proper opcode ) Tj
0 -13.92 TD 0.0579 Tc -0.2019 Tw (based on the actual operand value.) Tj
0 -29.28 TD /F0 13.92 Tf
0.082 Tc -0.1237 Tw (Opcodes of the S16 CPU) Tj
30.48 -52.8 TD /F0 12 Tf
0.0276 Tc 0.0564 Tw (Opcode Byte) Tj
109.92 -12.96 TD 0.0192 Tc 0.0648 Tw (Assembler Syntax) Tj
190.08 0 TD 0.048 Tc 0 Tw (Operation) Tj
-312.72 -12.96 TD /F1 12 Tf
0 Tc (1) Tj
41.76 0 TD (2) Tj
42.72 0 TD (3) Tj
-96.24 -24 TD (00) Tj
126.48 0 TD 0.06 Tc (HALT) Tj
120.48 0 TD 0.1018 Tc -0.2458 Tw (HALT until next interrupt \(if enabled\)) Tj
-246.96 -22.08 TD 0 Tc 0 Tw (01) Tj
126.48 0 TD (NOP) Tj
120.48 0 TD 0.0533 Tc -0.2933 Tw (Do nothing) Tj
-246.96 -21.84 TD 0 Tc 0 Tw (02) Tj
126.48 0 TD -0.12 Tw (JMP u) Tj
120.48 0 TD (PC := u) Tj
ET
71.76 92.16 0.48 117.6 re f
113.04 91.68 0.48 92.64 re f
155.76 91.68 0.48 92.64 re f
198.24 91.68 0.48 118.56 re f
318.72 91.68 0.48 118.56 re f
538.32 92.16 0.48 117.6 re f
71.76 210.24 m
71.76 209.76 l
538.8 209.76 l
538.8 210.24 l
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71.76 184.32 m
71.76 183.84 l
198.72 183.84 l
198.72 184.32 l
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72.24 159.6 m
72.24 159.12 l
538.32 159.12 l
538.32 159.6 l
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72.24 156.96 m
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538.32 156.48 l
538.32 156.96 l
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71.76 136.32 m
71.76 135.84 l
538.8 135.84 l
538.8 136.32 l
h
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71.76 114.24 m
71.76 113.76 l
538.8 113.76 l
538.8 114.24 l
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71.76 92.16 m
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78 654 TD
0 0 0 rg
/F1 12 Tf
0 Tc 0 Tw (03) Tj
41.28 0 TD (UL) Tj
42.72 0 TD (UH) Tj
42.48 0 TD 0.0267 Tc -0.1867 Tw (JMP RRNZ, u) Tj
120.48 0 TD 0.1029 Tc -0.2229 Tw (PC = u iff \(RR != 0\)) Tj
-246.96 -22.08 TD 0 Tc 0 Tw (04) Tj
41.28 0 TD (UL) Tj
42.72 0 TD (UH) Tj
42.48 0 TD 0.03 Tc -0.19 Tw (JMP RRZ, u) Tj
120.48 0 TD 0.0857 Tc -0.1657 Tw (PC = u iff \(RR == 0\)) Tj
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41.28 0 TD (UL) Tj
42.72 0 TD (UH) Tj
42.48 0 TD 0.096 Tc -0.096 Tw (CALL u) Tj
120.48 0 TD -0.015 Tc -0.0879 Tw (-\(SP\) = PC + 3; PC := u) Tj
-246.96 -22.08 TD 0 Tc 0 Tw (06) Tj
126.48 0 TD 0.06 Tc -0.06 Tw (CALL \(RR\)) Tj
120.48 0 TD -0.0141 Tc -0.0887 Tw (-\(SP\) = PC + 3; PC := RR) Tj
-246.96 -22.08 TD 0 Tc 0 Tw (07) Tj
126.48 0 TD -0.08 Tc (RET) Tj
120.48 0 TD -0.0267 Tc -0.0933 Tw (PC := \(SP\)+) Tj
-246.96 -21.84 TD 0 Tc 0 Tw (08) Tj
126.48 0 TD -0.24 Tw (MOVE \(SP\)+, RR) Tj
120.48 0 TD -0.0267 Tc -0.0933 Tw (RR := \(SP\)+) Tj
-246.96 -22.08 TD 0 Tc 0 Tw (09) Tj
126.48 0 TD -0.24 Tw (MOVE \(SP\)+, RS) Tj
120.48 0 TD 0.0417 Tc -0.1617 Tw (RR := \(SP\)+ \(sign extended\)) Tj
-246.96 -22.08 TD 0 Tc 0 Tw (0A) Tj
126.48 0 TD -0.24 Tw (MOVE \(SP\)+, RU) Tj
120.48 0 TD -0.0209 Tc -0.0391 Tw (RR := \(SP\)+ \(zero extended\)) Tj
-246.96 -21.84 TD 0 Tc 0 Tw (0B) Tj
126.48 0 TD -0.24 Tw (MOVE \(SP\)+, LL) Tj
120.48 0 TD -0.12 Tw (LL := \(SP\)+) Tj
-246.96 -22.08 TD 0 Tw (0C) Tj
126.48 0 TD -0.24 Tw (MOVE \(SP\)+, LS) Tj
120.48 0 TD 0.0417 Tc -0.1617 Tw (LL := \(SP\)+ \(sign extended\)) Tj
-246.96 -22.08 TD 0 Tc 0 Tw (0D) Tj
126.48 0 TD -0.24 Tw (MOVE \(SP\)+, LU) Tj
120.48 0 TD 0.0104 Tc -0.1904 Tw (LL := \(SP\)+ \(zero extended\)) Tj
-246.96 -21.84 TD 0 Tc 0 Tw (0E) Tj
126.48 0 TD -0.02 Tc -0.1 Tw (MOVE RR, -\(SP\)) Tj
120.48 0 TD -0.0533 Tc -0.0667 Tw (-\(SP\) := RR) Tj
-246.96 -22.08 TD 0 Tc 0 Tw (0F) Tj
126.48 0 TD -0.0218 Tc -0.2182 Tw (MOVE R, -\(SP\)) Tj
120.48 0 TD -0.06 Tc -0.06 Tw (-\(SP\) := R) Tj
-246.96 -22.08 TD 0 Tc 0 Tw (10) Tj
41.28 0 TD (UL) Tj
42.72 0 TD (UH) Tj
42.48 -11.04 TD 0.03 Tc -0.19 Tw (AND RR, #u) Tj
120.48 0 TD 0.06 Tc -0.18 Tw (RR := RR & u) Tj
-246.96 -10.8 TD 0 Tc 0 Tw (11) Tj
41.28 0 TD (U8) Tj
-41.28 -22.08 TD (12) Tj
41.28 0 TD (UL) Tj
42.72 0 TD (UH) Tj
42.48 -11.04 TD 0.0343 Tc -0.2143 Tw (OR RR, #u) Tj
120.48 0 TD 0.03 Tc -0.15 Tw (RR := RR | u) Tj
-246.96 -11.04 TD 0 Tc 0 Tw (13) Tj
41.28 0 TD (U8) Tj
-41.28 -21.84 TD (14) Tj
41.28 0 TD (UL) Tj
42.72 0 TD (UH) Tj
42.48 -11.04 TD -0.08 Tw (XOR RR, #u) Tj
120.48 0 TD 0.06 Tc -0.24 Tw (RR := RR ^ u) Tj
-246.96 -11.04 TD 0 Tc 0 Tw (15) Tj
41.28 0 TD (U8) Tj
-41.28 -22.08 TD (16) Tj
41.28 0 TD (SL) Tj
42.72 0 TD (SH) Tj
42.48 -11.04 TD -0.03 Tc -0.05 Tw (SEQ RR, #s) Tj
120.48 0 TD 0.1029 Tc -0.2229 Tw (RR := -1 iff \(RR == s\) else 0) Tj
-246.96 -10.8 TD 0 Tc 0 Tw (17) Tj
41.28 0 TD (S8) Tj
-41.28 -22.08 TD (18) Tj
41.28 0 TD (SL) Tj
42.72 0 TD (SH) Tj
42.48 -11.04 TD -0.03 Tc -0.05 Tw (SNE RR, #s) Tj
120.48 0 TD 0.1029 Tc -0.2229 Tw (RR := -1 iff \(RR != s\) else 0) Tj
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41.28 0 TD (S8) Tj
-41.28 -21.84 TD (1A) Tj
41.28 0 TD (SL) Tj
42.72 0 TD (SH) Tj
42.48 -11.04 TD -0.03 Tc -0.05 Tw (SGE RR, #s) Tj
120.48 0 TD 0.1091 Tc -0.2591 Tw (RR := -1 iff \(sRR >= s\) else 0) Tj
-246.96 -11.04 TD 0 Tc 0 Tw (1B) Tj
41.28 0 TD (S8) Tj
-41.28 -22.08 TD (1C) Tj
41.28 0 TD (SL) Tj
42.72 0 TD (SH) Tj
42.48 -11.04 TD -0.03 Tc -0.05 Tw (SGT RR, #s) Tj
120.48 0 TD 0.1029 Tc -0.2229 Tw (RR := -1 iff \(sRR > s\) else 0) Tj
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41.28 0 TD (S8) Tj
-16.8 621.84 TD /F0 12 Tf
0.0276 Tc 0.0564 Tw (Opcode Byte) Tj
109.92 -12.96 TD 0.0192 Tc 0.0648 Tw (Assembler Syntax) Tj
190.08 0 TD 0.048 Tc 0 Tw (Operation) Tj
-312.72 -12.96 TD /F1 12 Tf
0 Tc (1) Tj
41.76 0 TD (2) Tj
42.72 0 TD (3) Tj
ET
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113.04 73.68 0.48 620.64 re f
155.76 73.68 0.48 620.64 re f
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318.72 73.68 0.48 646.56 re f
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71.76 693.84 l
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198.72 694.32 l
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198.72 315.84 l
198.72 316.32 l
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538.8 294.24 l
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198.72 271.68 l
198.72 272.16 l
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71.76 249.84 l
538.8 249.84 l
538.8 250.32 l
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198.72 227.76 l
198.72 228.24 l
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198.72 183.84 l
198.72 184.32 l
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