library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use STD.TEXTIO.ALL;
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use STD.TEXTIO.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity BaudGen is
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entity BaudGen is
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Generic(bg_clock_freq : integer; bg_baud_rate : integer);
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Generic(bg_clock_freq : integer; bg_baud_rate : integer);
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Port( CLK_I : in std_logic;
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Port( CLK_I : in std_logic;
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RST_I : in std_logic;
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RST_I : in std_logic;
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CE_16 : out std_logic
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CE_16 : out std_logic
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);
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);
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end BaudGen;
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end BaudGen;
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architecture Behavioral of BaudGen is
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architecture Behavioral of BaudGen is
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-- divide bg_clock_freq and bg_baud_rate
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-- divide bg_clock_freq and bg_baud_rate
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-- by their common divisor...
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-- by their common divisor...
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--
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--
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function gcd(M, N: integer) return integer is
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function gcd(M, N: integer) return integer is
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begin
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begin
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if ((M mod N) = 0) then return N;
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if ((M mod N) = 0) then return N;
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else return gcd(N, M mod N);
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else return gcd(N, M mod N);
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end if;
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end if;
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end;
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end;
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constant common_div : integer := gcd(bg_clock_freq, 16 * bg_baud_rate);
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constant common_div : integer := gcd(bg_clock_freq, 16 * bg_baud_rate);
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constant clock_freq : integer := bg_clock_freq / common_div;
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constant clock_freq : integer := bg_clock_freq / common_div;
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constant baud_freq : integer := 16 * bg_baud_rate / common_div;
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constant baud_freq : integer := 16 * bg_baud_rate / common_div;
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constant limit : integer := clock_freq - baud_freq;
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constant limit : integer := clock_freq - baud_freq;
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signal COUNTER : integer range 0 to clock_freq - 1;
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signal COUNTER : integer range 0 to clock_freq - 1;
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begin
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begin
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process(CLK_I)
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process(CLK_I)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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CE_16 <= '0'; -- make CE_16 stay on for (at most) one cycle
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CE_16 <= '0'; -- make CE_16 stay on for (at most) one cycle
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if (RST_I = '1') then
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if (RST_I = '1') then
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COUNTER <= 0;
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COUNTER <= 0;
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elsif (COUNTER >= limit) then
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elsif (COUNTER >= limit) then
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CE_16 <= '1';
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CE_16 <= '1';
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COUNTER <= COUNTER - limit;
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COUNTER <= COUNTER - limit;
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else
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else
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COUNTER <= COUNTER + baud_freq;
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COUNTER <= COUNTER + baud_freq;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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