--
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--
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-- This is the top level VHDL file.
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-- This is the top level VHDL file.
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--
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--
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-- It iobufs for bidirational signals (towards an optional
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-- It iobufs for bidirational signals (towards an optional
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-- external fast SRAM.
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-- external fast SRAM.
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--
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--
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-- Pins fit the AVNET Virtex-E Evaluation board
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-- Pins fit the AVNET Virtex-E Evaluation board
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--
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--
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-- For other boards, change pin assignments in this file.
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-- For other boards, change pin assignments in this file.
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use work.cpu_pack.ALL;
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use work.cpu_pack.ALL;
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library UNISIM;
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library UNISIM;
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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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entity board_cpu is
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entity board_cpu is
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PORT ( CLK40 : in STD_LOGIC;
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PORT ( CLK40 : in STD_LOGIC;
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SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
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SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
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SER_IN : in STD_LOGIC;
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SER_IN : in STD_LOGIC;
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SER_OUT : out STD_LOGIC;
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SER_OUT : out STD_LOGIC;
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TEMP_SPO : in STD_LOGIC;
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TEMP_SPO : in STD_LOGIC;
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TEMP_SPI : out STD_LOGIC;
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TEMP_SPI : out STD_LOGIC;
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CLK_OUT : out STD_LOGIC;
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CLK_OUT : out STD_LOGIC;
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LED : out STD_LOGIC_VECTOR (7 downto 0);
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LED : out STD_LOGIC_VECTOR (7 downto 0);
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ENABLE_N : out STD_LOGIC;
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ENABLE_N : out STD_LOGIC;
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DEACTIVATE_N : out STD_LOGIC;
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DEACTIVATE_N : out STD_LOGIC;
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TEMP_CE : out STD_LOGIC;
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TEMP_CE : out STD_LOGIC;
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TEMP_SCLK : out STD_LOGIC;
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TEMP_SCLK : out STD_LOGIC;
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SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
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SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
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SEG2 : out STD_LOGIC_VECTOR (7 downto 0);
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SEG2 : out STD_LOGIC_VECTOR (7 downto 0);
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XM_ADR : out STD_LOGIC_VECTOR(14 downto 0);
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XM_ADR : out STD_LOGIC_VECTOR(14 downto 0);
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XM_CE_N : out STD_LOGIC;
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XM_CE_N : out STD_LOGIC;
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XM_OE_N : out STD_LOGIC;
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XM_OE_N : out STD_LOGIC;
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XM_WE_N : inout STD_LOGIC;
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XM_WE_N : inout STD_LOGIC;
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XM_DIO : inout STD_LOGIC_VECTOR(7 downto 0)
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XM_DIO : inout STD_LOGIC_VECTOR(7 downto 0)
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);
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);
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end board_cpu;
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end board_cpu;
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architecture behavioral of board_cpu is
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architecture behavioral of board_cpu is
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COMPONENT cpu
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COMPONENT cpu
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PORT( CLK_I : in STD_LOGIC;
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PORT( CLK_I : in STD_LOGIC;
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SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
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SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
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SER_IN : in STD_LOGIC;
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SER_IN : in STD_LOGIC;
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SER_OUT : out STD_LOGIC;
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SER_OUT : out STD_LOGIC;
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TEMP_SPO : in STD_LOGIC;
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TEMP_SPO : in STD_LOGIC;
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TEMP_SPI : out STD_LOGIC;
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TEMP_SPI : out STD_LOGIC;
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TEMP_CE : out STD_LOGIC;
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TEMP_CE : out STD_LOGIC;
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TEMP_SCLK : out STD_LOGIC;
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TEMP_SCLK : out STD_LOGIC;
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SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
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SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
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SEG2 : out STD_LOGIC_VECTOR( 7 downto 0);
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SEG2 : out STD_LOGIC_VECTOR( 7 downto 0);
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LED : out STD_LOGIC_VECTOR( 7 downto 0);
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LED : out STD_LOGIC_VECTOR( 7 downto 0);
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XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);
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XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);
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XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
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XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
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XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
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XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
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XM_WE : out STD_LOGIC;
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XM_WE : out STD_LOGIC;
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XM_CE : out STD_LOGIC
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XM_CE : out STD_LOGIC
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);
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);
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END COMPONENT;
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END COMPONENT;
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signal XM_WDAT : std_logic_vector( 7 downto 0);
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signal XM_WDAT : std_logic_vector( 7 downto 0);
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signal XM_RDAT : std_logic_vector( 7 downto 0);
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signal XM_RDAT : std_logic_vector( 7 downto 0);
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signal MEM_T : std_logic;
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signal MEM_T : std_logic;
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signal XM_WE : std_logic;
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signal XM_WE : std_logic;
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signal WE_N : std_logic;
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signal WE_N : std_logic;
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signal DEL_WE_N : std_logic;
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signal DEL_WE_N : std_logic;
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signal XM_CE : std_logic;
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signal XM_CE : std_logic;
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signal LCLK : std_logic;
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signal LCLK : std_logic;
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begin
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begin
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cp: cpu
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cp: cpu
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PORT MAP( CLK_I => CLK40,
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PORT MAP( CLK_I => CLK40,
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SWITCH => SWITCH,
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SWITCH => SWITCH,
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SER_IN => SER_IN,
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SER_IN => SER_IN,
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SER_OUT => SER_OUT,
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SER_OUT => SER_OUT,
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TEMP_SPO => TEMP_SPO,
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TEMP_SPO => TEMP_SPO,
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TEMP_SPI => TEMP_SPI,
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TEMP_SPI => TEMP_SPI,
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XM_ADR(14 downto 0) => XM_ADR,
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XM_ADR(14 downto 0) => XM_ADR,
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XM_ADR(15) => open,
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XM_ADR(15) => open,
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XM_RDAT => XM_RDAT,
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XM_RDAT => XM_RDAT,
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XM_WDAT => XM_WDAT,
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XM_WDAT => XM_WDAT,
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XM_WE => XM_WE,
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XM_WE => XM_WE,
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XM_CE => XM_CE,
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XM_CE => XM_CE,
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TEMP_CE => TEMP_CE,
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TEMP_CE => TEMP_CE,
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TEMP_SCLK => TEMP_SCLK,
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TEMP_SCLK => TEMP_SCLK,
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SEG1 => SEG1,
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SEG1 => SEG1,
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SEG2 => SEG2,
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SEG2 => SEG2,
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LED => LED
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LED => LED
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);
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);
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ENABLE_N <= '0';
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ENABLE_N <= '0';
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DEACTIVATE_N <= '1';
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DEACTIVATE_N <= '1';
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CLK_OUT <= LCLK;
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CLK_OUT <= LCLK;
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MEM_T <= DEL_WE_N; -- active low
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MEM_T <= DEL_WE_N; -- active low
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WE_N <= not XM_WE;
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WE_N <= not XM_WE;
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XM_OE_N <= XM_WE;
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XM_OE_N <= XM_WE;
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XM_CE_N <= not XM_CE;
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XM_CE_N <= not XM_CE;
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p147: iobuf PORT MAP(I => XM_WDAT(7), O => XM_RDAT(7), T => MEM_T, IO => XM_DIO(7));
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p147: iobuf PORT MAP(I => XM_WDAT(7), O => XM_RDAT(7), T => MEM_T, IO => XM_DIO(7));
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p144: iobuf PORT MAP(I => XM_WDAT(0), O => XM_RDAT(0), T => MEM_T, IO => XM_DIO(0));
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p144: iobuf PORT MAP(I => XM_WDAT(0), O => XM_RDAT(0), T => MEM_T, IO => XM_DIO(0));
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p142: iobuf PORT MAP(I => XM_WDAT(6), O => XM_RDAT(6), T => MEM_T, IO => XM_DIO(6));
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p142: iobuf PORT MAP(I => XM_WDAT(6), O => XM_RDAT(6), T => MEM_T, IO => XM_DIO(6));
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p141: iobuf PORT MAP(I => XM_WDAT(1), O => XM_RDAT(1), T => MEM_T, IO => XM_DIO(1));
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p141: iobuf PORT MAP(I => XM_WDAT(1), O => XM_RDAT(1), T => MEM_T, IO => XM_DIO(1));
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p140: iobuf PORT MAP(I => XM_WDAT(5), O => XM_RDAT(5), T => MEM_T, IO => XM_DIO(5));
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p140: iobuf PORT MAP(I => XM_WDAT(5), O => XM_RDAT(5), T => MEM_T, IO => XM_DIO(5));
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p139: iobuf PORT MAP(I => XM_WDAT(2), O => XM_RDAT(2), T => MEM_T, IO => XM_DIO(2));
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p139: iobuf PORT MAP(I => XM_WDAT(2), O => XM_RDAT(2), T => MEM_T, IO => XM_DIO(2));
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p133: iobuf PORT MAP(I => XM_WDAT(4), O => XM_RDAT(4), T => MEM_T, IO => XM_DIO(4));
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p133: iobuf PORT MAP(I => XM_WDAT(4), O => XM_RDAT(4), T => MEM_T, IO => XM_DIO(4));
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p131: iobuf PORT MAP(I => XM_WDAT(3), O => XM_RDAT(3), T => MEM_T, IO => XM_DIO(3));
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p131: iobuf PORT MAP(I => XM_WDAT(3), O => XM_RDAT(3), T => MEM_T, IO => XM_DIO(3));
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p63: iobuf PORT MAP(I => WE_N, O => DEL_WE_N, T => '0', IO => XM_WE_N);
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p63: iobuf PORT MAP(I => WE_N, O => DEL_WE_N, T => '0', IO => XM_WE_N);
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process(CLK40)
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process(CLK40)
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begin
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begin
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if (rising_edge(CLK40)) then
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if (rising_edge(CLK40)) then
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LCLK <= not LCLK;
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LCLK <= not LCLK;
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end if;
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end if;
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end process;
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end process;
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end behavioral;
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end behavioral;
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