library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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use work.cpu_pack.ALL;
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use work.cpu_pack.ALL;
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entity alu8 is
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entity alu8 is
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PORT( CLK_I : in std_logic;
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PORT( CLK_I : in std_logic;
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T2 : in std_logic;
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T2 : in std_logic;
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CLR : in std_logic;
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CLR : in std_logic;
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CE : in std_logic;
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CE : in std_logic;
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ALU_OP : in std_logic_vector( 4 downto 0);
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ALU_OP : in std_logic_vector( 4 downto 0);
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XX : in std_logic_vector(15 downto 0);
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XX : in std_logic_vector(15 downto 0);
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YY : in std_logic_vector(15 downto 0);
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YY : in std_logic_vector(15 downto 0);
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ZZ : out std_logic_vector(15 downto 0)
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ZZ : out std_logic_vector(15 downto 0)
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);
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);
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end alu8;
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end alu8;
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architecture Behavioral of alu8 is
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architecture Behavioral of alu8 is
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function sh_mask(Y : unsigned(3 downto 0);
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function sh_mask(Y : unsigned(3 downto 0);
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YMAX : unsigned(3 downto 0);
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YMAX : unsigned(3 downto 0);
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LR : std_logic;
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LR : std_logic;
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FILL : std_logic;
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FILL : std_logic;
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X : std_logic) return std_logic is
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X : std_logic) return std_logic is
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begin
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begin
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if (YMAX >= Y) then -- Y small
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if (YMAX >= Y) then -- Y small
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if (LR = '1') then return X; -- LSL
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if (LR = '1') then return X; -- LSL
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else return FILL; -- LSR
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else return FILL; -- LSR
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end if;
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end if;
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else -- Y big
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else -- Y big
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if (LR = '1') then return FILL; -- LSL
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if (LR = '1') then return FILL; -- LSL
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else return X; -- ASR/LSR
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else return X; -- ASR/LSR
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end if;
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end if;
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end if;
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end if;
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end;
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end;
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function b8(A : std_logic) return std_logic_vector is
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function b8(A : std_logic) return std_logic_vector is
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begin
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begin
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return A & A & A & A & A & A & A & A;
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return A & A & A & A & A & A & A & A;
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end;
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end;
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function b16(A : std_logic) return std_logic_vector is
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function b16(A : std_logic) return std_logic_vector is
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begin
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begin
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return b8(A) & b8(A);
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return b8(A) & b8(A);
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end;
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end;
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function aoxn(A : std_logic_vector(3 downto 0)) return std_logic is
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function aoxn(A : std_logic_vector(3 downto 0)) return std_logic is
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begin
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begin
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case A is
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case A is
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-- and
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-- and
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when "0000" => return '0';
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when "0000" => return '0';
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when "0001" => return '0';
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when "0001" => return '0';
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when "0010" => return '0';
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when "0010" => return '0';
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when "0011" => return '1';
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when "0011" => return '1';
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-- or
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-- or
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when "0100" => return '0';
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when "0100" => return '0';
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when "0101" => return '1';
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when "0101" => return '1';
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when "0110" => return '1';
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when "0110" => return '1';
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when "0111" => return '1';
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when "0111" => return '1';
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-- xor
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-- xor
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when "1000" => return '0';
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when "1000" => return '0';
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when "1001" => return '1';
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when "1001" => return '1';
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when "1010" => return '1';
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when "1010" => return '1';
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when "1011" => return '0';
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when "1011" => return '0';
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-- not Y
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-- not Y
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when "1100" => return '1';
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when "1100" => return '1';
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when "1101" => return '0';
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when "1101" => return '0';
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when "1110" => return '1';
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when "1110" => return '1';
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when others => return '0';
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when others => return '0';
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end case;
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end case;
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end;
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end;
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signal MD_OR : std_logic_vector(15 downto 0); -- Multiplicator/Divisor
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signal MD_OR : std_logic_vector(15 downto 0); -- Multiplicator/Divisor
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signal PROD_REM : std_logic_vector(31 downto 0);
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signal PROD_REM : std_logic_vector(31 downto 0);
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signal MD_OP : std_logic; -- operation D/M, S/U
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signal MD_OP : std_logic; -- operation D/M, S/U
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signal QP_NEG : std_logic; -- product / quotient negative
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signal QP_NEG : std_logic; -- product / quotient negative
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signal RM_NEG : std_logic; -- remainder negative
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signal RM_NEG : std_logic; -- remainder negative
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begin
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begin
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alumux: process(ALU_OP, MD_OP, XX, YY, QP_NEG, RM_NEG, PROD_REM)
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alumux: process(ALU_OP, MD_OP, XX, YY, QP_NEG, RM_NEG, PROD_REM)
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variable MASKED_X : std_logic_vector(15 downto 0);
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variable MASKED_X : std_logic_vector(15 downto 0);
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variable SCNT : unsigned(3 downto 0);
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variable SCNT : unsigned(3 downto 0);
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variable SFILL : std_logic;
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variable SFILL : std_logic;
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variable ROL1 : std_logic_vector(15 downto 0);
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variable ROL1 : std_logic_vector(15 downto 0);
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variable ROL2 : std_logic_vector(15 downto 0);
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variable ROL2 : std_logic_vector(15 downto 0);
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variable ROL4 : std_logic_vector(15 downto 0);
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variable ROL4 : std_logic_vector(15 downto 0);
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variable ROL8 : std_logic_vector(15 downto 0);
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variable ROL8 : std_logic_vector(15 downto 0);
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variable X_GE_Y : std_logic; -- signed X >= Y
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variable X_GE_Y : std_logic; -- signed X >= Y
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variable X_HS_Y : std_logic; -- unsigned X >= Y
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variable X_HS_Y : std_logic; -- unsigned X >= Y
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variable X_HSGE_Y : std_logic; -- any X >= Y
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variable X_HSGE_Y : std_logic; -- any X >= Y
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variable X_EQ_Y : std_logic; -- signed X == Y
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variable X_EQ_Y : std_logic; -- signed X == Y
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variable X_CMP_Y : std_logic;
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variable X_CMP_Y : std_logic;
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begin
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begin
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MASKED_X := XX and b16(ALU_OP(0));
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MASKED_X := XX and b16(ALU_OP(0));
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SFILL := ALU_OP(0) and XX(15);
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SFILL := ALU_OP(0) and XX(15);
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if (ALU_OP(1) = '1') then -- LSL
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if (ALU_OP(1) = '1') then -- LSL
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SCNT := UNSIGNED(YY(3 downto 0));
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SCNT := UNSIGNED(YY(3 downto 0));
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else -- LSR / ASR
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else -- LSR / ASR
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SCNT := "0000" - UNSIGNED(YY(3 downto 0));
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SCNT := "0000" - UNSIGNED(YY(3 downto 0));
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end if;
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end if;
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if (SCNT(0) = '0') then ROL1 := XX;
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if (SCNT(0) = '0') then ROL1 := XX;
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else ROL1 := XX(14 downto 0) & XX(15);
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else ROL1 := XX(14 downto 0) & XX(15);
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end if;
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end if;
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if (SCNT(1) = '0') then ROL2 := ROL1;
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if (SCNT(1) = '0') then ROL2 := ROL1;
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else ROL2 := ROL1(13 downto 0) & ROL1(15 downto 14);
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else ROL2 := ROL1(13 downto 0) & ROL1(15 downto 14);
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end if;
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end if;
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if (SCNT(2) = '0') then ROL4 := ROL2;
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if (SCNT(2) = '0') then ROL4 := ROL2;
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else ROL4 := ROL2(11 downto 0) & ROL2(15 downto 12);
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else ROL4 := ROL2(11 downto 0) & ROL2(15 downto 12);
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end if;
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end if;
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if (SCNT(3) = '0') then ROL8 := ROL4;
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if (SCNT(3) = '0') then ROL8 := ROL4;
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else ROL8 := ROL4(7 downto 0) & ROL4(15 downto 8);
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else ROL8 := ROL4(7 downto 0) & ROL4(15 downto 8);
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end if;
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end if;
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if (XX = YY) then X_EQ_Y := '1';
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if (XX = YY) then X_EQ_Y := '1';
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else X_EQ_Y := '0';
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else X_EQ_Y := '0';
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end if;
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end if;
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if (UNSIGNED(XX) >= UNSIGNED(YY)) then X_HSGE_Y := '1';
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if (UNSIGNED(XX) >= UNSIGNED(YY)) then X_HSGE_Y := '1';
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else X_HSGE_Y := '0';
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else X_HSGE_Y := '0';
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end if;
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end if;
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if (XX(15) /= YY(15)) then -- different sign/high bit
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if (XX(15) /= YY(15)) then -- different sign/high bit
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X_HS_Y := XX(15); -- X ia bigger iff high bit set
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X_HS_Y := XX(15); -- X ia bigger iff high bit set
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X_GE_Y := YY(15); -- X is bigger iff Y negative
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X_GE_Y := YY(15); -- X is bigger iff Y negative
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else -- same sign/high bit: GE == HS
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else -- same sign/high bit: GE == HS
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X_HS_Y := X_HSGE_Y;
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X_HS_Y := X_HSGE_Y;
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X_GE_Y := X_HSGE_Y;
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X_GE_Y := X_HSGE_Y;
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end if;
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end if;
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case ALU_OP is
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case ALU_OP is
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when ALU_X_HS_Y => X_CMP_Y := X_HS_Y;
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when ALU_X_HS_Y => X_CMP_Y := X_HS_Y;
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when ALU_X_LO_Y => X_CMP_Y := not X_HS_Y;
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when ALU_X_LO_Y => X_CMP_Y := not X_HS_Y;
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when ALU_X_HI_Y => X_CMP_Y := X_HS_Y and not X_EQ_Y;
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when ALU_X_HI_Y => X_CMP_Y := X_HS_Y and not X_EQ_Y;
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when ALU_X_LS_Y => X_CMP_Y := not (X_HS_Y and not X_EQ_Y);
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when ALU_X_LS_Y => X_CMP_Y := not (X_HS_Y and not X_EQ_Y);
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when ALU_X_GE_Y => X_CMP_Y := X_GE_Y;
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when ALU_X_GE_Y => X_CMP_Y := X_GE_Y;
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when ALU_X_LT_Y => X_CMP_Y := not X_GE_Y;
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when ALU_X_LT_Y => X_CMP_Y := not X_GE_Y;
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when ALU_X_GT_Y => X_CMP_Y := X_GE_Y and not X_EQ_Y;
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when ALU_X_GT_Y => X_CMP_Y := X_GE_Y and not X_EQ_Y;
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when ALU_X_LE_Y => X_CMP_Y := not (X_GE_Y and not X_EQ_Y);
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when ALU_X_LE_Y => X_CMP_Y := not (X_GE_Y and not X_EQ_Y);
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when ALU_X_EQ_Y => X_CMP_Y := X_EQ_Y;
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when ALU_X_EQ_Y => X_CMP_Y := X_EQ_Y;
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when others => X_CMP_Y := not X_EQ_Y;
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when others => X_CMP_Y := not X_EQ_Y;
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end case;
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end case;
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ZZ <= X"0000";
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ZZ <= X"0000";
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case ALU_OP is
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case ALU_OP is
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when ALU_X_HS_Y | ALU_X_LO_Y | ALU_X_HI_Y | ALU_X_LS_Y |
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when ALU_X_HS_Y | ALU_X_LO_Y | ALU_X_HI_Y | ALU_X_LS_Y |
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ALU_X_GE_Y | ALU_X_LT_Y | ALU_X_GT_Y | ALU_X_LE_Y |
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ALU_X_GE_Y | ALU_X_LT_Y | ALU_X_GT_Y | ALU_X_LE_Y |
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ALU_X_EQ_Y | ALU_X_NE_Y =>
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ALU_X_EQ_Y | ALU_X_NE_Y =>
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ZZ <= b16(X_CMP_Y);
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ZZ <= b16(X_CMP_Y);
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when ALU_NEG_Y | ALU_X_SUB_Y =>
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when ALU_NEG_Y | ALU_X_SUB_Y =>
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ZZ <= MASKED_X - YY;
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ZZ <= MASKED_X - YY;
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when ALU_MOVE_Y | ALU_X_ADD_Y =>
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when ALU_MOVE_Y | ALU_X_ADD_Y =>
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ZZ <= MASKED_X + YY;
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ZZ <= MASKED_X + YY;
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when ALU_X_AND_Y | ALU_X_OR_Y | ALU_X_XOR_Y | ALU_NOT_Y =>
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when ALU_X_AND_Y | ALU_X_OR_Y | ALU_X_XOR_Y | ALU_NOT_Y =>
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for i in 0 to 15 loop
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for i in 0 to 15 loop
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ZZ(i) <= aoxn(ALU_OP(1 downto 0) & XX(i) & YY(i));
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ZZ(i) <= aoxn(ALU_OP(1 downto 0) & XX(i) & YY(i));
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end loop;
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end loop;
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when ALU_X_LSR_Y | ALU_X_ASR_Y | ALU_X_LSL_Y =>
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when ALU_X_LSR_Y | ALU_X_ASR_Y | ALU_X_LSL_Y =>
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for i in 0 to 15 loop
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for i in 0 to 15 loop
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ZZ(i) <= sh_mask(SCNT, CONV_UNSIGNED(i, 4),
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ZZ(i) <= sh_mask(SCNT, CONV_UNSIGNED(i, 4),
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ALU_OP(1), SFILL, ROL8(i));
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ALU_OP(1), SFILL, ROL8(i));
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end loop;
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end loop;
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when ALU_X_MIX_Y =>
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when ALU_X_MIX_Y =>
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ZZ(15 downto 8) <= YY(7 downto 0);
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ZZ(15 downto 8) <= YY(7 downto 0);
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ZZ( 7 downto 0) <= XX(7 downto 0);
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ZZ( 7 downto 0) <= XX(7 downto 0);
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when ALU_MUL_IU | ALU_MUL_IS |
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when ALU_MUL_IU | ALU_MUL_IS |
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ALU_DIV_IU | ALU_DIV_IS | ALU_MD_STP => -- mult/div ini/step
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ALU_DIV_IU | ALU_DIV_IS | ALU_MD_STP => -- mult/div ini/step
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ZZ <= PROD_REM(15 downto 0);
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ZZ <= PROD_REM(15 downto 0);
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when ALU_MD_FIN => -- mult/div
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when ALU_MD_FIN => -- mult/div
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if (QP_NEG = '0') then ZZ <= PROD_REM(15 downto 0);
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if (QP_NEG = '0') then ZZ <= PROD_REM(15 downto 0);
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else ZZ <= X"0000" - PROD_REM(15 downto 0);
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else ZZ <= X"0000" - PROD_REM(15 downto 0);
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end if;
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end if;
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when others => -- modulo
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when others => -- modulo
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if (RM_NEG = '0') then ZZ <= PROD_REM(31 downto 16);
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if (RM_NEG = '0') then ZZ <= PROD_REM(31 downto 16);
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else ZZ <= X"0000" - PROD_REM(31 downto 16);
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else ZZ <= X"0000" - PROD_REM(31 downto 16);
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end if;
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end if;
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end case;
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end case;
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end process;
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end process;
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muldiv: process(CLK_I)
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muldiv: process(CLK_I)
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variable POS_YY : std_logic_vector(15 downto 0);
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variable POS_YY : std_logic_vector(15 downto 0);
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variable POS_XX : std_logic_vector(15 downto 0);
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variable POS_XX : std_logic_vector(15 downto 0);
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variable DIFF : std_logic_vector(16 downto 0);
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variable DIFF : std_logic_vector(16 downto 0);
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variable SUM : std_logic_vector(16 downto 0);
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variable SUM : std_logic_vector(16 downto 0);
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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if (T2 = '1') then
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if (T2 = '1') then
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if (CLR = '1') then
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if (CLR = '1') then
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PROD_REM <= X"00000000"; -- product/remainder
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PROD_REM <= X"00000000"; -- product/remainder
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MD_OR <= X"0000"; -- multiplicator/divisor
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MD_OR <= X"0000"; -- multiplicator/divisor
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MD_OP <= '0'; -- mult(0)/div(1)
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MD_OP <= '0'; -- mult(0)/div(1)
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QP_NEG <= '0'; -- quotient/product negative
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QP_NEG <= '0'; -- quotient/product negative
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RM_NEG <= '0'; -- remainder negative
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RM_NEG <= '0'; -- remainder negative
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elsif (CE = '1') then
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elsif (CE = '1') then
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SUM := ('0' & PROD_REM(31 downto 16)) + ('0' & MD_OR);
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SUM := ('0' & PROD_REM(31 downto 16)) + ('0' & MD_OR);
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DIFF := ('0' & PROD_REM(30 downto 15)) - ('0' & MD_OR);
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DIFF := ('0' & PROD_REM(30 downto 15)) - ('0' & MD_OR);
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if (XX(15) = '0') then POS_XX := XX;
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if (XX(15) = '0') then POS_XX := XX;
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else POS_XX := X"0000" - XX;
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else POS_XX := X"0000" - XX;
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end if;
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end if;
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if (YY(15) = '0') then POS_YY := YY;
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if (YY(15) = '0') then POS_YY := YY;
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else POS_YY := X"0000" - YY;
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else POS_YY := X"0000" - YY;
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end if;
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end if;
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case ALU_OP is
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case ALU_OP is
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when ALU_MUL_IU | ALU_MUL_IS | ALU_DIV_IU | ALU_DIV_IS =>
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when ALU_MUL_IU | ALU_MUL_IS | ALU_DIV_IU | ALU_DIV_IS =>
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MD_OP <= ALU_OP(1); -- div / mult
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MD_OP <= ALU_OP(1); -- div / mult
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MD_OR <= POS_YY; -- multiplicator/divisor
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MD_OR <= POS_YY; -- multiplicator/divisor
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QP_NEG <= ALU_OP(0) and (XX(15) xor YY(15));
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QP_NEG <= ALU_OP(0) and (XX(15) xor YY(15));
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RM_NEG <= ALU_OP(0) and XX(15);
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RM_NEG <= ALU_OP(0) and XX(15);
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PROD_REM <= X"0000" & POS_XX;
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PROD_REM <= X"0000" & POS_XX;
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when ALU_MD_STP =>
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when ALU_MD_STP =>
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if (MD_OP = '0') then -- multiplication step
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if (MD_OP = '0') then -- multiplication step
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PROD_REM(15 downto 0) <= PROD_REM(16 downto 1);
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PROD_REM(15 downto 0) <= PROD_REM(16 downto 1);
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if (PROD_REM(0) = '0') then
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if (PROD_REM(0) = '0') then
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PROD_REM(31 downto 15) <=
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PROD_REM(31 downto 15) <=
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'0' & PROD_REM(31 downto 16);
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'0' & PROD_REM(31 downto 16);
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else
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else
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PROD_REM(31 downto 15) <= SUM;
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PROD_REM(31 downto 15) <= SUM;
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end if;
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end if;
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else -- division step
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else -- division step
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if (DIFF(16) = '1') then -- carry: small remainder
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if (DIFF(16) = '1') then -- carry: small remainder
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PROD_REM(31 downto 16) <= PROD_REM(30 downto 15);
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PROD_REM(31 downto 16) <= PROD_REM(30 downto 15);
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else
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else
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PROD_REM(31 downto 16) <= DIFF(15 downto 0);
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PROD_REM(31 downto 16) <= DIFF(15 downto 0);
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end if;
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end if;
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PROD_REM(15 downto 1) <= PROD_REM(14 downto 0);
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PROD_REM(15 downto 1) <= PROD_REM(14 downto 0);
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PROD_REM(0) <= not DIFF(16);
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PROD_REM(0) <= not DIFF(16);
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end if;
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end if;
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when others =>
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when others =>
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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