JDF F
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JDF F
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// Created by Project Navigator ver 1.0
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// Created by Project Navigator ver 1.0
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PROJECT cpu16
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PROJECT cpu16
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DESIGN cpu16 Normal
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DESIGN cpu16 Normal
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DEVFAM virtexe
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DEVFAM virtexe
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DEVFAMTIME 1064066933
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DEVFAMTIME 1064066933
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DEVICE xcv100e
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DEVICE xcv100e
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DEVICETIME 1064066933
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DEVICETIME 1064066933
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DEVPKG pq240
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DEVPKG pq240
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DEVPKGTIME 1064066933
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DEVPKGTIME 1064066933
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DEVSPEED -6
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DEVSPEED -6
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DEVSPEEDTIME 1064065691
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DEVSPEEDTIME 1064065691
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FLOW XST VHDL
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FLOW XST VHDL
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FLOWTIME 0
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FLOWTIME 0
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STIMULUS test.vhd Normal
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STIMULUS test.vhd Normal
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STIMULUS cpu_test.vhd Normal
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STIMULUS cpu_test.vhd Normal
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MODULE memory.vhd
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MODULE memory.vhd
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MODSTYLE memory Normal
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MODSTYLE memory Normal
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MODULE uart_rx.vhd
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MODULE uart_rx.vhd
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MODSTYLE uart_rx Normal
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MODSTYLE uart_rx Normal
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MODULE uart_tx.vhd
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MODULE uart_tx.vhd
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MODSTYLE uart_tx Normal
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MODSTYLE uart_tx Normal
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MODULE alu8.vhd
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MODULE alu8.vhd
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MODSTYLE alu8 Normal
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MODSTYLE alu8 Normal
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MODULE cpu.vhd
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MODULE cpu.vhd
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MODSTYLE cpu16 Normal
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MODSTYLE cpu16 Normal
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MODULE temperature.vhd
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MODULE temperature.vhd
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MODSTYLE temperature Normal
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MODSTYLE temperature Normal
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MODULE cpu_engine.vhd
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MODULE cpu_engine.vhd
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MODSTYLE cpu_engine Normal
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MODSTYLE cpu_engine Normal
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MODULE data_core.vhd
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MODULE data_core.vhd
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MODSTYLE data_core Normal
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MODSTYLE data_core Normal
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MODULE uart.vhd
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MODULE uart.vhd
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MODSTYLE uart Normal
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MODSTYLE uart Normal
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MODULE uart._baudgen.vhd
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MODULE uart._baudgen.vhd
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MODSTYLE uart_baudgen Normal
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MODSTYLE uart_baudgen Normal
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MODULE opcode_decoder.vhd
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MODULE opcode_decoder.vhd
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MODSTYLE opcode_decoder Normal
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MODSTYLE opcode_decoder Normal
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MODULE opcode_fetch.vhd
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MODULE opcode_fetch.vhd
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MODSTYLE opcode_fetch Normal
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MODSTYLE opcode_fetch Normal
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MODULE select_yy.vhd
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MODULE select_yy.vhd
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MODSTYLE select_yy Normal
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MODSTYLE select_yy Normal
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MODULE Board_cpu.vhd
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MODULE Board_cpu.vhd
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MODSTYLE board_cpu Normal
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MODSTYLE board_cpu Normal
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MODULE BaudGen.vhd
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MODULE BaudGen.vhd
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MODSTYLE baudgen Normal
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MODSTYLE baudgen Normal
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MODULE input_output.vhd
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MODULE input_output.vhd
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MODSTYLE input_output Normal
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MODSTYLE input_output Normal
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MODULE ds1722.vhd
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MODULE ds1722.vhd
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MODSTYLE ds1722 Normal
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MODSTYLE ds1722 Normal
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MODULE bin_to_7segment.vhd
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MODULE bin_to_7segment.vhd
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MODSTYLE bin_to_7segment Normal
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MODSTYLE bin_to_7segment Normal
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LIBFILE mem_content.vhd work ***
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LIBFILE mem_content.vhd work ***
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LIBFILE cpu_pack.vhd work ***
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LIBFILE cpu_pack.vhd work ***
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DEPASSOC board_cpu board_cpu.ucf SYSTEM
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DEPASSOC board_cpu board_cpu.ucf SYSTEM
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[Normal]
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[Normal]
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p_ModelSimSignalWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False
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p_ModelSimSignalWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False
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p_ModelSimStructWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False
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p_ModelSimStructWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False
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_SynthExtractROM=xstvhd, virtexe, Schematic.t_synthesize, 1064066560, False
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_SynthExtractROM=xstvhd, virtexe, Schematic.t_synthesize, 1064066560, False
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[STRATEGY-LIST]
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[STRATEGY-LIST]
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Normal=True
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Normal=True
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