library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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use work.cpu_pack.ALL;
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use work.cpu_pack.ALL;
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entity cpu_engine is
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entity cpu_engine is
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PORT( -- WISHBONE interface
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PORT( -- WISHBONE interface
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CLK_I : in std_logic;
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CLK_I : in std_logic;
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DAT_I : in std_logic_vector( 7 downto 0);
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DAT_I : in std_logic_vector( 7 downto 0);
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DAT_O : out std_logic_vector( 7 downto 0);
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DAT_O : out std_logic_vector( 7 downto 0);
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RST_I : in std_logic;
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RST_I : in std_logic;
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ACK_I : in std_logic;
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ACK_I : in std_logic;
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ADR_O : out std_logic_vector(15 downto 0);
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ADR_O : out std_logic_vector(15 downto 0);
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CYC_O : out std_logic;
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CYC_O : out std_logic;
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STB_O : out std_logic;
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STB_O : out std_logic;
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TGA_O : out std_logic_vector( 0 downto 0); -- '1' if I/O
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TGA_O : out std_logic_vector( 0 downto 0); -- '1' if I/O
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WE_O : out std_logic;
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WE_O : out std_logic;
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INT : in std_logic;
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INT : in std_logic;
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HALT : out std_logic;
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HALT : out std_logic;
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-- debug signals
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-- debug signals
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--
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--
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Q_PC : out std_logic_vector(15 downto 0);
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Q_PC : out std_logic_vector(15 downto 0);
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Q_OPC : out std_logic_vector( 7 downto 0);
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Q_OPC : out std_logic_vector( 7 downto 0);
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Q_CAT : out op_category;
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Q_CAT : out op_category;
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Q_IMM : out std_logic_vector(15 downto 0);
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Q_IMM : out std_logic_vector(15 downto 0);
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Q_CYC : out cycle;
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Q_CYC : out cycle;
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-- select signals
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-- select signals
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Q_SX : out std_logic_vector(1 downto 0);
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Q_SX : out std_logic_vector(1 downto 0);
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Q_SY : out std_logic_vector(3 downto 0);
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Q_SY : out std_logic_vector(3 downto 0);
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Q_OP : out std_logic_vector(4 downto 0);
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Q_OP : out std_logic_vector(4 downto 0);
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Q_SA : out std_logic_vector(4 downto 0);
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Q_SA : out std_logic_vector(4 downto 0);
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Q_SMQ : out std_logic;
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Q_SMQ : out std_logic;
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-- write enable/select signal
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-- write enable/select signal
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Q_WE_RR : out std_logic;
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Q_WE_RR : out std_logic;
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Q_WE_LL : out std_logic;
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Q_WE_LL : out std_logic;
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Q_WE_SP : out SP_OP;
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Q_WE_SP : out SP_OP;
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Q_RR : out std_logic_vector(15 downto 0);
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Q_RR : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_SP : out std_logic_vector(15 downto 0)
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Q_SP : out std_logic_vector(15 downto 0)
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);
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);
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end cpu_engine;
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end cpu_engine;
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architecture Behavioral of cpu_engine is
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architecture Behavioral of cpu_engine is
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-- Unfortunately, the on-chip memory needs a clock to read data.
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-- Unfortunately, the on-chip memory needs a clock to read data.
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-- Therefore we cannot make it wishbone compliant without a speed penalty.
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-- Therefore we cannot make it wishbone compliant without a speed penalty.
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-- We avoid this problem by making the on-chip memory part of the CPU.
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-- We avoid this problem by making the on-chip memory part of the CPU.
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-- However, as a consequence, you cannot DMA to the on-chip memory.
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-- However, as a consequence, you cannot DMA to the on-chip memory.
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--
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--
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-- The on-chip memory is 8K, so that you can run a test SoC without external
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-- The on-chip memory is 8K, so that you can run a test SoC without external
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-- memory. For bigger applications, you should use external ROM and RAM and
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-- memory. For bigger applications, you should use external ROM and RAM and
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-- remove the internal memory entirely (setting EXTERN accordingly).
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-- remove the internal memory entirely (setting EXTERN accordingly).
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--
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--
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COMPONENT memory
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COMPONENT memory
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PORT( CLK_I : IN std_logic;
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PORT( CLK_I : IN std_logic;
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T2 : IN std_logic;
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T2 : IN std_logic;
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CE : IN std_logic;
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CE : IN std_logic;
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PC : IN std_logic_vector(15 downto 0);
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PC : IN std_logic_vector(15 downto 0);
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ADR : IN std_logic_vector(15 downto 0);
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ADR : IN std_logic_vector(15 downto 0);
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WR : IN std_logic;
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WR : IN std_logic;
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WDAT : IN std_logic_vector(7 downto 0);
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WDAT : IN std_logic_vector(7 downto 0);
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OPC : OUT std_logic_vector(7 downto 0);
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OPC : OUT std_logic_vector(7 downto 0);
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RDAT : OUT std_logic_vector(7 downto 0)
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RDAT : OUT std_logic_vector(7 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT opcode_fetch
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COMPONENT opcode_fetch
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PORT( CLK_I : IN std_logic;
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PORT( CLK_I : IN std_logic;
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T2 : IN std_logic;
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T2 : IN std_logic;
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CLR : IN std_logic;
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CLR : IN std_logic;
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CE : IN std_logic;
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CE : IN std_logic;
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PC_OP : IN std_logic_vector(2 downto 0);
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PC_OP : IN std_logic_vector(2 downto 0);
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JDATA : IN std_logic_vector(15 downto 0);
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JDATA : IN std_logic_vector(15 downto 0);
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RR : IN std_logic_vector(15 downto 0);
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RR : IN std_logic_vector(15 downto 0);
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RDATA : IN std_logic_vector(7 downto 0);
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RDATA : IN std_logic_vector(7 downto 0);
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PC : OUT std_logic_vector(15 downto 0)
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PC : OUT std_logic_vector(15 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT opcode_decoder
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COMPONENT opcode_decoder
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PORT( CLK_I : IN std_logic;
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PORT( CLK_I : IN std_logic;
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T2 : IN std_logic;
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T2 : IN std_logic;
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CLR : IN std_logic;
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CLR : IN std_logic;
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CE : IN std_logic;
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CE : IN std_logic;
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OPCODE : in std_logic_vector(7 downto 0);
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OPCODE : in std_logic_vector(7 downto 0);
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OP_CYC : in cycle;
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OP_CYC : in cycle;
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INT : in std_logic;
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INT : in std_logic;
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RRZ : in std_logic;
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RRZ : in std_logic;
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OP_CAT : out op_category;
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OP_CAT : out op_category;
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-- select signals
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-- select signals
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D_SX : out std_logic_vector(1 downto 0); -- ALU select X
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D_SX : out std_logic_vector(1 downto 0); -- ALU select X
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D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
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D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
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D_OP : out std_logic_vector(4 downto 0); -- ALU operation
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D_OP : out std_logic_vector(4 downto 0); -- ALU operation
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D_SA : out std_logic_vector(4 downto 0); -- select address
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D_SA : out std_logic_vector(4 downto 0); -- select address
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D_SMQ : out std_logic;
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D_SMQ : out std_logic;
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-- write enable/select signal
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-- write enable/select signal
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D_WE_RR : out std_logic;
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D_WE_RR : out std_logic;
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D_WE_LL : out std_logic;
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D_WE_LL : out std_logic;
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D_WE_SP : out SP_OP;
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D_WE_SP : out SP_OP;
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D_RD_O : out std_logic;
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D_RD_O : out std_logic;
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D_WE_O : out std_logic;
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D_WE_O : out std_logic;
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D_LOCK : out std_logic;
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D_LOCK : out std_logic;
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-- input/output
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-- input/output
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D_IO : out std_logic;
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D_IO : out std_logic;
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PC_OP : out std_logic_vector(2 downto 0);
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PC_OP : out std_logic_vector(2 downto 0);
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LAST_M : out std_logic;
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LAST_M : out std_logic;
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HLT : out std_logic
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HLT : out std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT data_core
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COMPONENT data_core
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PORT( CLK_I : in std_logic;
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PORT( CLK_I : in std_logic;
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T2 : in std_logic;
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T2 : in std_logic;
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CLR : in std_logic;
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CLR : in std_logic;
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CE : in std_logic;
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CE : in std_logic;
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-- select signals
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-- select signals
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SX : in std_logic_vector( 1 downto 0);
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SX : in std_logic_vector( 1 downto 0);
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SY : in std_logic_vector( 3 downto 0);
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SY : in std_logic_vector( 3 downto 0);
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OP : in std_logic_vector( 4 downto 0); -- alu op
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OP : in std_logic_vector( 4 downto 0); -- alu op
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PC : in std_logic_vector(15 downto 0); -- PC
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PC : in std_logic_vector(15 downto 0); -- PC
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QU : in std_logic_vector( 3 downto 0); -- quick operand
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QU : in std_logic_vector( 3 downto 0); -- quick operand
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SA : in std_logic_vector(4 downto 0); -- select address
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SA : in std_logic_vector(4 downto 0); -- select address
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SMQ : in std_logic; -- select MQ (H/L)
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SMQ : in std_logic; -- select MQ (H/L)
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-- write enable/select signal
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-- write enable/select signal
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WE_RR : in std_logic;
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WE_RR : in std_logic;
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WE_LL : in std_logic;
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WE_LL : in std_logic;
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WE_SP : in SP_OP;
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WE_SP : in SP_OP;
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IMM : in std_logic_vector(15 downto 0); -- immediate data
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IMM : in std_logic_vector(15 downto 0); -- immediate data
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RDAT : in std_logic_vector( 7 downto 0); -- data from memory/IO
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RDAT : in std_logic_vector( 7 downto 0); -- data from memory/IO
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ADR : out std_logic_vector(15 downto 0); -- memory/IO address
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ADR : out std_logic_vector(15 downto 0); -- memory/IO address
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MQ : out std_logic_vector( 7 downto 0); -- data to memory/IO
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MQ : out std_logic_vector( 7 downto 0); -- data to memory/IO
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Q_RR : out std_logic_vector(15 downto 0);
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Q_RR : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_SP : out std_logic_vector(15 downto 0)
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Q_SP : out std_logic_vector(15 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- global signals
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-- global signals
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signal CE : std_logic;
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signal CE : std_logic;
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signal T2 : std_logic;
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signal T2 : std_logic;
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-- memory signals
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-- memory signals
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signal WDAT : std_logic_vector(7 downto 0);
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signal WDAT : std_logic_vector(7 downto 0);
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signal RDAT : std_logic_vector(7 downto 0);
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signal RDAT : std_logic_vector(7 downto 0);
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signal M_PC : std_logic_vector(15 downto 0);
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signal M_PC : std_logic_vector(15 downto 0);
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signal M_OPC : std_logic_vector(7 downto 0);
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signal M_OPC : std_logic_vector(7 downto 0);
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-- decoder signals
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-- decoder signals
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--
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--
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signal D_CAT : op_category;
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signal D_CAT : op_category;
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signal D_OPC : std_logic_vector(7 downto 0);
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signal D_OPC : std_logic_vector(7 downto 0);
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signal D_CYC : cycle;
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signal D_CYC : cycle;
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signal D_PC : std_logic_vector(15 downto 0); -- debug signal
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signal D_PC : std_logic_vector(15 downto 0); -- debug signal
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signal D_PC_OP : std_logic_vector( 2 downto 0);
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signal D_PC_OP : std_logic_vector( 2 downto 0);
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signal D_LAST_M : std_logic;
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signal D_LAST_M : std_logic;
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signal D_IO : std_logic;
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signal D_IO : std_logic;
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-- select signals
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-- select signals
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signal D_SX : std_logic_vector(1 downto 0);
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signal D_SX : std_logic_vector(1 downto 0);
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signal D_SY : std_logic_vector(3 downto 0);
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signal D_SY : std_logic_vector(3 downto 0);
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signal D_OP : std_logic_vector(4 downto 0);
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signal D_OP : std_logic_vector(4 downto 0);
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signal D_SA : std_logic_vector(4 downto 0);
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signal D_SA : std_logic_vector(4 downto 0);
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signal D_SMQ : std_logic;
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signal D_SMQ : std_logic;
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-- write enable/select signals
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-- write enable/select signals
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signal D_WE_RR : std_logic;
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signal D_WE_RR : std_logic;
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signal D_WE_LL : std_logic;
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signal D_WE_LL : std_logic;
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signal D_WE_SP : SP_OP;
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signal D_WE_SP : SP_OP;
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signal D_RD_O : std_logic;
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signal D_RD_O : std_logic;
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signal D_WE_O : std_logic;
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signal D_WE_O : std_logic;
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signal D_LOCK : std_logic; -- first cycle
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signal D_LOCK : std_logic; -- first cycle
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signal LM_WE : std_logic;
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signal LM_WE : std_logic;
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-- core signals
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-- core signals
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--
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--
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signal C_IMM : std_logic_vector(15 downto 0);
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signal C_IMM : std_logic_vector(15 downto 0);
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signal ADR : std_logic_vector(15 downto 0);
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signal ADR : std_logic_vector(15 downto 0);
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signal C_CYC : cycle; -- debug signal
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signal C_CYC : cycle; -- debug signal
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signal C_PC : std_logic_vector(15 downto 0); -- debug signal
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signal C_PC : std_logic_vector(15 downto 0); -- debug signal
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signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
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signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
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signal C_RR : std_logic_vector(15 downto 0);
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signal C_RR : std_logic_vector(15 downto 0);
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signal RRZ : std_logic;
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signal RRZ : std_logic;
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signal OC_JD : std_logic_vector(15 downto 0);
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signal OC_JD : std_logic_vector(15 downto 0);
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-- select signals
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-- select signals
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signal C_SX : std_logic_vector(1 downto 0);
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signal C_SX : std_logic_vector(1 downto 0);
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signal C_SY : std_logic_vector(3 downto 0);
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signal C_SY : std_logic_vector(3 downto 0);
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signal C_OP : std_logic_vector(4 downto 0);
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signal C_OP : std_logic_vector(4 downto 0);
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signal C_SA : std_logic_vector(4 downto 0);
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signal C_SA : std_logic_vector(4 downto 0);
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signal C_SMQ : std_logic;
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signal C_SMQ : std_logic;
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signal C_WE_RR : std_logic;
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signal C_WE_RR : std_logic;
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signal C_WE_LL : std_logic;
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signal C_WE_LL : std_logic;
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signal C_WE_SP : SP_OP;
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signal C_WE_SP : SP_OP;
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signal XM_OPC : std_logic_vector(7 downto 0);
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signal XM_OPC : std_logic_vector(7 downto 0);
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signal LM_OPC : std_logic_vector(7 downto 0);
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signal LM_OPC : std_logic_vector(7 downto 0);
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signal LM_RDAT : std_logic_vector(7 downto 0);
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signal LM_RDAT : std_logic_vector(7 downto 0);
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signal XM_RDAT : std_logic_vector(7 downto 0);
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signal XM_RDAT : std_logic_vector(7 downto 0);
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signal C_IO : std_logic;
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signal C_IO : std_logic;
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signal C_RD_O : std_logic;
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signal C_RD_O : std_logic;
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signal C_WE_O : std_logic;
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signal C_WE_O : std_logic;
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-- signals to remember, whether the previous read cycle
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-- signals to remember, whether the previous read cycle
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-- addressed internal memory or external memory
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-- addressed internal memory or external memory
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--
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--
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signal OPCS : std_logic; -- '1' if opcode from external memory
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signal OPCS : std_logic; -- '1' if opcode from external memory
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signal RDATS : std_logic; -- '1' if data from external memory
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signal RDATS : std_logic; -- '1' if data from external memory
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signal EXTERN : std_logic; -- '1' if opcode or data from external memory
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signal EXTERN : std_logic; -- '1' if opcode or data from external memory
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|
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begin
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begin
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memo: memory
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memo: memory
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => T2,
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T2 => T2,
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CE => CE,
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CE => CE,
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|
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-- read in T1
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-- read in T1
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PC => M_PC,
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PC => M_PC,
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OPC => LM_OPC,
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OPC => LM_OPC,
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|
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-- read or written in T2
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-- read or written in T2
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ADR => ADR,
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ADR => ADR,
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WR => LM_WE,
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WR => LM_WE,
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WDAT => WDAT,
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WDAT => WDAT,
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RDAT => LM_RDAT
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RDAT => LM_RDAT
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);
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);
|
|
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ocf: opcode_fetch
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ocf: opcode_fetch
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => T2,
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T2 => T2,
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CLR => RST_I,
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CLR => RST_I,
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CE => CE,
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CE => CE,
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PC_OP => D_PC_OP,
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PC_OP => D_PC_OP,
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JDATA => OC_JD,
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JDATA => OC_JD,
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RR => C_RR,
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RR => C_RR,
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RDATA => RDAT,
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RDATA => RDAT,
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PC => M_PC
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PC => M_PC
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);
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);
|
|
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opdec: opcode_decoder
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opdec: opcode_decoder
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => T2,
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T2 => T2,
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CLR => RST_I,
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CLR => RST_I,
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CE => CE,
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CE => CE,
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OPCODE => D_OPC,
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OPCODE => D_OPC,
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OP_CYC => D_CYC,
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OP_CYC => D_CYC,
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INT => INT,
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INT => INT,
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RRZ => RRZ,
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RRZ => RRZ,
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|
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OP_CAT => D_CAT,
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OP_CAT => D_CAT,
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|
|
-- select signals
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-- select signals
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D_SX => D_SX,
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D_SX => D_SX,
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D_SY => D_SY,
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D_SY => D_SY,
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D_OP => D_OP,
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D_OP => D_OP,
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D_SA => D_SA,
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D_SA => D_SA,
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D_SMQ => D_SMQ,
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D_SMQ => D_SMQ,
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|
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-- write enable/select signal
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-- write enable/select signal
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D_WE_RR => D_WE_RR,
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D_WE_RR => D_WE_RR,
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D_WE_LL => D_WE_LL,
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D_WE_LL => D_WE_LL,
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D_WE_SP => D_WE_SP,
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D_WE_SP => D_WE_SP,
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D_RD_O => D_RD_O,
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D_RD_O => D_RD_O,
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D_WE_O => D_WE_O,
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D_WE_O => D_WE_O,
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D_LOCK => D_LOCK,
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D_LOCK => D_LOCK,
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|
|
D_IO => D_IO,
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D_IO => D_IO,
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|
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PC_OP => D_PC_OP,
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PC_OP => D_PC_OP,
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LAST_M => D_LAST_M,
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LAST_M => D_LAST_M,
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HLT => HALT
|
HLT => HALT
|
);
|
);
|
|
|
dcore: data_core
|
dcore: data_core
|
PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => T2,
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T2 => T2,
|
CLR => RST_I,
|
CLR => RST_I,
|
CE => CE,
|
CE => CE,
|
|
|
-- select signals
|
-- select signals
|
SX => C_SX,
|
SX => C_SX,
|
SY => C_SY,
|
SY => C_SY,
|
OP => C_OP,
|
OP => C_OP,
|
PC => C_PC,
|
PC => C_PC,
|
QU => C_OPC(3 downto 0),
|
QU => C_OPC(3 downto 0),
|
SA => C_SA,
|
SA => C_SA,
|
SMQ => C_SMQ,
|
SMQ => C_SMQ,
|
|
|
-- write enable/select signal
|
-- write enable/select signal
|
WE_RR => C_WE_RR,
|
WE_RR => C_WE_RR,
|
WE_LL => C_WE_LL,
|
WE_LL => C_WE_LL,
|
WE_SP => C_WE_SP,
|
WE_SP => C_WE_SP,
|
|
|
IMM => C_IMM,
|
IMM => C_IMM,
|
RDAT => RDAT,
|
RDAT => RDAT,
|
ADR => ADR,
|
ADR => ADR,
|
MQ => WDAT,
|
MQ => WDAT,
|
|
|
Q_RR => C_RR,
|
Q_RR => C_RR,
|
Q_LL => Q_LL,
|
Q_LL => Q_LL,
|
Q_SP => Q_SP
|
Q_SP => Q_SP
|
);
|
);
|
|
|
CE <= ACK_I or not EXTERN;
|
CE <= ACK_I or not EXTERN;
|
TGA_O(0) <= T2 and C_IO;
|
TGA_O(0) <= T2 and C_IO;
|
WE_O <= T2 and C_WE_O;
|
WE_O <= T2 and C_WE_O;
|
STB_O <= EXTERN;
|
STB_O <= EXTERN;
|
CYC_O <= EXTERN;
|
CYC_O <= EXTERN;
|
|
|
Q_RR <= C_RR;
|
Q_RR <= C_RR;
|
RRZ <= '1' when (C_RR = X"0000") else '0';
|
RRZ <= '1' when (C_RR = X"0000") else '0';
|
OC_JD <= M_OPC & C_IMM(7 downto 0);
|
OC_JD <= M_OPC & C_IMM(7 downto 0);
|
|
|
Q_PC <= C_PC;
|
Q_PC <= C_PC;
|
Q_OPC <= C_OPC;
|
Q_OPC <= C_OPC;
|
Q_CYC <= C_CYC;
|
Q_CYC <= C_CYC;
|
Q_IMM <= C_IMM;
|
Q_IMM <= C_IMM;
|
|
|
-- select signals
|
-- select signals
|
Q_SX <= C_SX;
|
Q_SX <= C_SX;
|
Q_SY <= C_SY;
|
Q_SY <= C_SY;
|
Q_OP <= C_OP;
|
Q_OP <= C_OP;
|
Q_SA <= C_SA;
|
Q_SA <= C_SA;
|
Q_SMQ <= C_SMQ;
|
Q_SMQ <= C_SMQ;
|
|
|
-- write enable/select signal (debug)
|
-- write enable/select signal (debug)
|
Q_WE_RR <= C_WE_RR;
|
Q_WE_RR <= C_WE_RR;
|
Q_WE_LL <= C_WE_LL;
|
Q_WE_LL <= C_WE_LL;
|
Q_WE_SP <= C_WE_SP;
|
Q_WE_SP <= C_WE_SP;
|
|
|
DAT_O <= WDAT;
|
DAT_O <= WDAT;
|
|
|
process(CLK_I)
|
process(CLK_I)
|
begin
|
begin
|
if (rising_edge(CLK_I)) then
|
if (rising_edge(CLK_I)) then
|
if (RST_I = '1') then T2 <= '0';
|
if (RST_I = '1') then T2 <= '0';
|
elsif (CE = '1') then T2 <= not T2;
|
elsif (CE = '1') then T2 <= not T2;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
process(T2, M_PC, ADR, C_IO, C_RD_O, C_WE_O)
|
process(T2, M_PC, ADR, C_IO, C_RD_O, C_WE_O)
|
begin
|
begin
|
if (T2 = '0') then -- opcode fetch
|
if (T2 = '0') then -- opcode fetch
|
EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
|
EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
|
-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
|
-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
|
-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
|
-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
|
-- B EXTERN <= '1'; -- no internal memory
|
-- B EXTERN <= '1'; -- no internal memory
|
else -- data or I/O
|
else -- data or I/O
|
EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 8Kx8 internal memory
|
EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 8Kx8 internal memory
|
-- A EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 512x8 internal memory
|
-- A EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 512x8 internal memory
|
-- A ADR(12) or ADR(11) or ADR(10) or ADR(9) or
|
-- A ADR(12) or ADR(11) or ADR(10) or ADR(9) or
|
-- B EXTERN <= ('1' or -- no internal memory
|
-- B EXTERN <= ('1' or -- no internal memory
|
C_IO) and (C_RD_O or C_WE_O);
|
C_IO) and (C_RD_O or C_WE_O);
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- remember whether access is to internal or to external (incl I/O) memory.
|
-- remember whether access is to internal or to external (incl I/O) memory.
|
-- clock read data to XM_OPCODE in T1 or to XM_RDAT in T2
|
-- clock read data to XM_OPCODE in T1 or to XM_RDAT in T2
|
--
|
--
|
process(CLK_I)
|
process(CLK_I)
|
begin
|
begin
|
if (rising_edge(CLK_I)) then
|
if (rising_edge(CLK_I)) then
|
if (CE = '1') then
|
if (CE = '1') then
|
if (T2 = '0') then
|
if (T2 = '0') then
|
OPCS <= EXTERN;
|
OPCS <= EXTERN;
|
XM_OPC <= DAT_I;
|
XM_OPC <= DAT_I;
|
else
|
else
|
RDATS <= EXTERN;
|
RDATS <= EXTERN;
|
XM_RDAT <= DAT_I;
|
XM_RDAT <= DAT_I;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
|
M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
|
ADR_O <= M_PC when (T2 = '0') else ADR;
|
ADR_O <= M_PC when (T2 = '0') else ADR;
|
RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
|
RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
|
|
|
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
|
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
|
begin
|
begin
|
if (RST_I = '1') then
|
if (RST_I = '1') then
|
|
|
C_PC <= X"0000";
|
C_PC <= X"0000";
|
C_OPC <= X"01";
|
C_OPC <= X"01";
|
C_CYC <= M1;
|
C_CYC <= M1;
|
|
|
C_SX <= "00";
|
C_SX <= "00";
|
C_SY <= "0000";
|
C_SY <= "0000";
|
C_OP <= "00000";
|
C_OP <= "00000";
|
C_SA <= "00000";
|
C_SA <= "00000";
|
C_SMQ <= '0';
|
C_SMQ <= '0';
|
C_WE_RR <= '0';
|
C_WE_RR <= '0';
|
C_WE_LL <= '0';
|
C_WE_LL <= '0';
|
C_WE_SP <= SP_NOP;
|
C_WE_SP <= SP_NOP;
|
C_IO <= '0';
|
C_IO <= '0';
|
C_RD_O <= '0';
|
C_RD_O <= '0';
|
C_WE_O <= '0';
|
C_WE_O <= '0';
|
LM_WE <= '0';
|
LM_WE <= '0';
|
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
|
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
|
C_CYC <= D_CYC;
|
C_CYC <= D_CYC;
|
Q_CAT <= D_CAT;
|
Q_CAT <= D_CAT;
|
C_PC <= D_PC;
|
C_PC <= D_PC;
|
C_OPC <= D_OPC;
|
C_OPC <= D_OPC;
|
C_SX <= D_SX;
|
C_SX <= D_SX;
|
C_SY <= D_SY;
|
C_SY <= D_SY;
|
C_OP <= D_OP;
|
C_OP <= D_OP;
|
C_SA <= D_SA;
|
C_SA <= D_SA;
|
C_SMQ <= D_SMQ;
|
C_SMQ <= D_SMQ;
|
C_WE_RR <= D_WE_RR;
|
C_WE_RR <= D_WE_RR;
|
C_WE_LL <= D_WE_LL;
|
C_WE_LL <= D_WE_LL;
|
C_WE_SP <= D_WE_SP;
|
C_WE_SP <= D_WE_SP;
|
C_IO <= D_IO;
|
C_IO <= D_IO;
|
C_RD_O <= D_RD_O;
|
C_RD_O <= D_RD_O;
|
C_WE_O <= D_WE_O;
|
C_WE_O <= D_WE_O;
|
LM_WE <= D_WE_O and not D_IO;
|
LM_WE <= D_WE_O and not D_IO;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
|
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
|
begin
|
begin
|
if (RST_I = '1') then
|
if (RST_I = '1') then
|
D_PC <= X"0000";
|
D_PC <= X"0000";
|
D_OPC <= X"01";
|
D_OPC <= X"01";
|
D_CYC <= M1;
|
D_CYC <= M1;
|
C_IMM <= X"FFFF";
|
C_IMM <= X"FFFF";
|
|
|
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
|
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
|
if (D_LAST_M = '1') then -- D goes to M1
|
if (D_LAST_M = '1') then -- D goes to M1
|
-- signals valid for entire opcode... PORTATO FUORI
|
-- signals valid for entire opcode... PORTATO FUORI
|
D_OPC <= M_OPC;
|
D_OPC <= M_OPC;
|
D_PC <= M_PC;
|
D_PC <= M_PC;
|
D_CYC <= M1;
|
D_CYC <= M1;
|
else
|
else
|
case D_CYC is
|
case D_CYC is
|
when M1 => D_CYC <= M2; -- C goes to M1
|
when M1 => D_CYC <= M2; -- C goes to M1
|
C_IMM <= X"00" & M_OPC;
|
C_IMM <= X"00" & M_OPC;
|
when M2 => D_CYC <= M3;
|
when M2 => D_CYC <= M3;
|
C_IMM(15 downto 8) <= M_OPC;
|
C_IMM(15 downto 8) <= M_OPC;
|
when M3 => D_CYC <= M4;
|
when M3 => D_CYC <= M4;
|
when M4 => D_CYC <= M5;
|
when M4 => D_CYC <= M5;
|
when M5 => D_CYC <= M1;
|
when M5 => D_CYC <= M1;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
