-- Package File Template
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-- Package File Template
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--
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--
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-- Purpose: This package defines supplemental types, subtypes,
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-- Purpose: This package defines supplemental types, subtypes,
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-- constants, and functions
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-- constants, and functions
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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package cpu_pack is
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package cpu_pack is
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type cycle is ( M1, M2, M3, M4, M5 );
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type cycle is ( M1, M2, M3, M4, M5 );
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type op_category is (
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type op_category is (
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INTR,
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INTR,
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HALT_WAIT,
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HALT_WAIT,
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-- 0X
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-- 0X
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HALT,
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HALT,
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NOP,
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NOP,
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JMP_i,
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JMP_i,
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JMP_RRNZ_i,
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JMP_RRNZ_i,
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JMP_RRZ_i,
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JMP_RRZ_i,
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CALL_i,
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CALL_i,
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CALL_RR,
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CALL_RR,
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RET,
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RET,
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MOVE_SPi_RR,
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MOVE_SPi_RR,
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MOVE_SPi_RS,
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MOVE_SPi_RS,
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MOVE_SPi_RU,
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MOVE_SPi_RU,
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MOVE_SPi_LL,
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MOVE_SPi_LL,
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MOVE_SPi_LS,
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MOVE_SPi_LS,
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MOVE_SPi_LU,
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MOVE_SPi_LU,
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MOVE_RR_dSP,
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MOVE_RR_dSP,
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MOVE_R_dSP,
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MOVE_R_dSP,
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-- 1X
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-- 1X
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AND_RR_i,
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AND_RR_i,
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OR_RR_i,
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OR_RR_i,
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XOR_RR_i,
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XOR_RR_i,
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SEQ_RR_i,
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SEQ_RR_i,
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SNE_RR_i,
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SNE_RR_i,
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SGE_RR_i,
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SGE_RR_i,
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SGT_RR_i,
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SGT_RR_i,
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SLE_RR_i,
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SLE_RR_i,
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-- 2X
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-- 2X
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SLT_RR_i,
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SLT_RR_i,
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SHS_RR_i,
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SHS_RR_i,
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SHI_RR_i,
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SHI_RR_i,
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SLS_RR_i,
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SLS_RR_i,
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SLO_RR_i,
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SLO_RR_i,
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CLRW_dSP,
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CLRW_dSP,
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CLRB_dSP,
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CLRB_dSP,
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IN_ci_RU,
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IN_ci_RU,
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OUT_R_ci,
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OUT_R_ci,
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-- 3X
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-- 3X
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AND_LL_RR,
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AND_LL_RR,
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OR_LL_RR,
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OR_LL_RR,
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XOR_LL_RR,
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XOR_LL_RR,
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SEQ_LL_RR,
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SEQ_LL_RR,
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SNE_LL_RR,
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SNE_LL_RR,
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SGE_LL_RR,
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SGE_LL_RR,
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SGT_LL_RR,
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SGT_LL_RR,
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SLE_LL_RR,
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SLE_LL_RR,
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SLT_LL_RR,
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SLT_LL_RR,
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SHS_LL_RR,
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SHS_LL_RR,
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SHI_LL_RR,
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SHI_LL_RR,
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SLS_LL_RR,
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SLS_LL_RR,
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SLO_LL_RR,
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SLO_LL_RR,
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LNOT_RR,
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LNOT_RR,
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NEG_RR,
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NEG_RR,
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NOT_RR,
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NOT_RR,
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-- 4X
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-- 4X
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MOVE_LL_RR,
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MOVE_LL_RR,
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MOVE_LL_cRR,
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MOVE_LL_cRR,
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MOVE_L_cRR,
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MOVE_L_cRR,
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MOVE_RR_LL,
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MOVE_RR_LL,
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MOVE_RR_cLL,
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MOVE_RR_cLL,
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MOVE_R_cLL,
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MOVE_R_cLL,
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MOVE_cRR_RR,
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MOVE_cRR_RR,
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MOVE_cRR_RS,
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MOVE_cRR_RS,
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MOVE_cRR_RU,
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MOVE_cRR_RU,
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MOVE_ci_RR,
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MOVE_ci_RR,
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MOVE_ci_RS,
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MOVE_ci_RS,
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MOVE_ci_RU,
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MOVE_ci_RU,
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MOVE_ci_LL,
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MOVE_ci_LL,
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MOVE_ci_LS,
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MOVE_ci_LS,
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MOVE_ci_LU,
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MOVE_ci_LU,
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MOVE_RR_SP,
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MOVE_RR_SP,
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-- 5X
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-- 5X
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LSL_RR_i,
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LSL_RR_i,
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ASR_RR_i,
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ASR_RR_i,
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LSR_RR_i,
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LSR_RR_i,
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LSL_LL_RR,
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LSL_LL_RR,
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ASR_LL_RR,
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ASR_LL_RR,
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LSR_LL_RR,
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LSR_LL_RR,
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ADD_LL_RR,
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ADD_LL_RR,
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SUB_LL_RR,
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SUB_LL_RR,
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MOVE_RR_ci,
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MOVE_RR_ci,
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MOVE_R_ci,
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MOVE_R_ci,
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MOVE_RR_uSP,
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MOVE_RR_uSP,
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MOVE_R_uSP,
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MOVE_R_uSP,
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-- 6X
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-- 6X
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MOVE_uSP_RR,
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MOVE_uSP_RR,
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MOVE_uSP_RS,
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MOVE_uSP_RS,
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MOVE_uSP_RU,
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MOVE_uSP_RU,
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MOVE_uSP_LL,
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MOVE_uSP_LL,
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MOVE_uSP_LS,
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MOVE_uSP_LS,
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MOVE_uSP_LU,
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MOVE_uSP_LU,
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LEA_uSP_RR,
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LEA_uSP_RR,
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MOVE_dRR_dLL,
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MOVE_dRR_dLL,
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MOVE_RRi_LLi,
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MOVE_RRi_LLi,
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-- 7X
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-- 7X
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MUL_IS,
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MUL_IS,
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MUL_IU,
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MUL_IU,
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DIV_IS,
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DIV_IS,
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DIV_IU,
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DIV_IU,
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MD_STEP,
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MD_STEP,
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MD_FIN,
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MD_FIN,
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MOD_FIN,
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MOD_FIN,
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EI,
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EI,
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RETI,
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RETI,
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DI,
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DI,
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-- 9X ... FX
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-- 9X ... FX
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ADD_RR_I,
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ADD_RR_I,
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SUB_RR_I,
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SUB_RR_I,
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MOVE_I_RR,
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MOVE_I_RR,
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ADD_SP_I,
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ADD_SP_I,
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SEQ_LL_I,
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SEQ_LL_I,
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MOVE_I_LL,
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MOVE_I_LL,
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undef );
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undef );
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type SP_OP is ( SP_NOP, SP_INC, SP_LOAD );
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type SP_OP is ( SP_NOP, SP_INC, SP_LOAD );
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-- ALU codes
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-- ALU codes
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--
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--
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constant ALU_X_HS_Y : std_logic_vector(4 downto 0) := "00000";
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constant ALU_X_HS_Y : std_logic_vector(4 downto 0) := "00000";
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constant ALU_X_LO_Y : std_logic_vector(4 downto 0) := "00001";
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constant ALU_X_LO_Y : std_logic_vector(4 downto 0) := "00001";
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constant ALU_X_HI_Y : std_logic_vector(4 downto 0) := "00010";
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constant ALU_X_HI_Y : std_logic_vector(4 downto 0) := "00010";
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constant ALU_X_LS_Y : std_logic_vector(4 downto 0) := "00011";
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constant ALU_X_LS_Y : std_logic_vector(4 downto 0) := "00011";
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constant ALU_X_GE_Y : std_logic_vector(4 downto 0) := "00100";
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constant ALU_X_GE_Y : std_logic_vector(4 downto 0) := "00100";
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constant ALU_X_LT_Y : std_logic_vector(4 downto 0) := "00101";
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constant ALU_X_LT_Y : std_logic_vector(4 downto 0) := "00101";
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constant ALU_X_GT_Y : std_logic_vector(4 downto 0) := "00110";
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constant ALU_X_GT_Y : std_logic_vector(4 downto 0) := "00110";
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constant ALU_X_LE_Y : std_logic_vector(4 downto 0) := "00111";
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constant ALU_X_LE_Y : std_logic_vector(4 downto 0) := "00111";
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constant ALU_X_EQ_Y : std_logic_vector(4 downto 0) := "01000";
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constant ALU_X_EQ_Y : std_logic_vector(4 downto 0) := "01000";
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constant ALU_X_NE_Y : std_logic_vector(4 downto 0) := "01001";
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constant ALU_X_NE_Y : std_logic_vector(4 downto 0) := "01001";
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constant ALU_NEG_Y : std_logic_vector(4 downto 0) := "01100";
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constant ALU_NEG_Y : std_logic_vector(4 downto 0) := "01100";
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constant ALU_X_SUB_Y : std_logic_vector(4 downto 0) := "01101";
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constant ALU_X_SUB_Y : std_logic_vector(4 downto 0) := "01101";
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constant ALU_MOVE_Y : std_logic_vector(4 downto 0) := "01110";
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constant ALU_MOVE_Y : std_logic_vector(4 downto 0) := "01110";
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constant ALU_X_ADD_Y : std_logic_vector(4 downto 0) := "01111";
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constant ALU_X_ADD_Y : std_logic_vector(4 downto 0) := "01111";
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constant ALU_X_AND_Y : std_logic_vector(4 downto 0) := "10000";
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constant ALU_X_AND_Y : std_logic_vector(4 downto 0) := "10000";
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constant ALU_X_OR_Y : std_logic_vector(4 downto 0) := "10001";
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constant ALU_X_OR_Y : std_logic_vector(4 downto 0) := "10001";
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constant ALU_X_XOR_Y : std_logic_vector(4 downto 0) := "10010";
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constant ALU_X_XOR_Y : std_logic_vector(4 downto 0) := "10010";
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constant ALU_NOT_Y : std_logic_vector(4 downto 0) := "10011";
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constant ALU_NOT_Y : std_logic_vector(4 downto 0) := "10011";
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constant ALU_X_LSR_Y : std_logic_vector(4 downto 0) := "10100";
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constant ALU_X_LSR_Y : std_logic_vector(4 downto 0) := "10100";
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constant ALU_X_ASR_Y : std_logic_vector(4 downto 0) := "10101";
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constant ALU_X_ASR_Y : std_logic_vector(4 downto 0) := "10101";
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constant ALU_X_LSL_Y : std_logic_vector(4 downto 0) := "10110";
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constant ALU_X_LSL_Y : std_logic_vector(4 downto 0) := "10110";
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constant ALU_X_MIX_Y : std_logic_vector(4 downto 0) := "10111";
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constant ALU_X_MIX_Y : std_logic_vector(4 downto 0) := "10111";
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constant ALU_MUL_IU : std_logic_vector(4 downto 0) := "11000";
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constant ALU_MUL_IU : std_logic_vector(4 downto 0) := "11000";
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constant ALU_MUL_IS : std_logic_vector(4 downto 0) := "11001";
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constant ALU_MUL_IS : std_logic_vector(4 downto 0) := "11001";
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constant ALU_DIV_IU : std_logic_vector(4 downto 0) := "11010";
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constant ALU_DIV_IU : std_logic_vector(4 downto 0) := "11010";
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constant ALU_DIV_IS : std_logic_vector(4 downto 0) := "11011";
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constant ALU_DIV_IS : std_logic_vector(4 downto 0) := "11011";
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constant ALU_MD_STP : std_logic_vector(4 downto 0) := "11100";
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constant ALU_MD_STP : std_logic_vector(4 downto 0) := "11100";
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constant ALU_MD_FIN : std_logic_vector(4 downto 0) := "11101";
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constant ALU_MD_FIN : std_logic_vector(4 downto 0) := "11101";
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constant ALU_MOD_FIN : std_logic_vector(4 downto 0) := "11110";
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constant ALU_MOD_FIN : std_logic_vector(4 downto 0) := "11110";
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constant ALU_ANY : std_logic_vector(4 downto 0) := ALU_X_AND_Y;
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constant ALU_ANY : std_logic_vector(4 downto 0) := ALU_X_AND_Y;
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--------------------------------------------------------------
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--------------------------------------------------------------
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constant SA_43_0 : std_logic_vector(1 downto 0) := "00";
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constant SA_43_0 : std_logic_vector(1 downto 0) := "00";
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constant SA_43_FFFF : std_logic_vector(1 downto 0) := "01"; -- last bit 1 !!!
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constant SA_43_FFFF : std_logic_vector(1 downto 0) := "01"; -- last bit 1 !!!
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constant SA_43_I16 : std_logic_vector(1 downto 0) := "10";
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constant SA_43_I16 : std_logic_vector(1 downto 0) := "10";
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constant SA_43_I8S : std_logic_vector(1 downto 0) := "11";
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constant SA_43_I8S : std_logic_vector(1 downto 0) := "11";
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constant SA_21_0 : std_logic_vector(1 downto 0) := "00";
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constant SA_21_0 : std_logic_vector(1 downto 0) := "00";
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constant SA_21_LL : std_logic_vector(1 downto 0) := "01";
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constant SA_21_LL : std_logic_vector(1 downto 0) := "01";
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constant SA_21_RR : std_logic_vector(1 downto 0) := "10";
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constant SA_21_RR : std_logic_vector(1 downto 0) := "10";
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constant SA_21_SP : std_logic_vector(1 downto 0) := "11";
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constant SA_21_SP : std_logic_vector(1 downto 0) := "11";
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constant ADR_cSP_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_SP & '0';
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constant ADR_cSP_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_SP & '0';
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constant ADR_cRR_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_RR & '0';
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constant ADR_cRR_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_RR & '0';
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constant ADR_cLL_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_LL & '0';
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constant ADR_cLL_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_LL & '0';
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constant ADR_cI16_L : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_0 & '0';
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constant ADR_cI16_L : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_0 & '0';
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constant ADR_16SP_L : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_SP & '0';
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constant ADR_16SP_L : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_SP & '0';
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constant ADR_8SP_L : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_SP & '0';
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constant ADR_8SP_L : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_SP & '0';
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constant ADR_IO : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_0 & '0';
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constant ADR_IO : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_0 & '0';
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constant ADR_cSP_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_SP & '1';
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constant ADR_cSP_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_SP & '1';
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constant ADR_cRR_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_RR & '1';
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constant ADR_cRR_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_RR & '1';
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constant ADR_cLL_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_LL & '1';
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constant ADR_cLL_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_LL & '1';
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constant ADR_cI16_H : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_0 & '1';
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constant ADR_cI16_H : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_0 & '1';
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constant ADR_16SP_H : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_SP & '1';
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constant ADR_16SP_H : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_SP & '1';
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constant ADR_8SP_H : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_SP & '1';
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constant ADR_8SP_H : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_SP & '1';
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constant ADR_dSP : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_SP & '0';
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constant ADR_dSP : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_SP & '0';
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constant ADR_dRR : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_RR & '0';
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constant ADR_dRR : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_RR & '0';
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constant ADR_dLL : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_LL & '0';
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constant ADR_dLL : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_LL & '0';
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constant ADR_SPi : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_SP & '1';
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constant ADR_SPi : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_SP & '1';
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constant ADR_RRi : std_logic_vector(4 downto 0) := ADR_cRR_L;
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constant ADR_RRi : std_logic_vector(4 downto 0) := ADR_cRR_L;
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constant ADR_LLi : std_logic_vector(4 downto 0) := ADR_cLL_L;
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constant ADR_LLi : std_logic_vector(4 downto 0) := ADR_cLL_L;
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--------------------------------------------------------------
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--------------------------------------------------------------
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constant SX_LL : std_logic_vector(1 downto 0) := "00";
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constant SX_LL : std_logic_vector(1 downto 0) := "00";
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constant SX_RR : std_logic_vector(1 downto 0) := "01";
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constant SX_RR : std_logic_vector(1 downto 0) := "01";
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constant SX_SP : std_logic_vector(1 downto 0) := "10";
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constant SX_SP : std_logic_vector(1 downto 0) := "10";
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constant SX_PC : std_logic_vector(1 downto 0) := "11";
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constant SX_PC : std_logic_vector(1 downto 0) := "11";
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constant SX_ANY : std_logic_vector(1 downto 0) := SX_RR;
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constant SX_ANY : std_logic_vector(1 downto 0) := SX_RR;
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--------------------------------------------------------------
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--------------------------------------------------------------
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constant SY_SY0 : std_logic_vector(3 downto 0) := "0000";
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constant SY_SY0 : std_logic_vector(3 downto 0) := "0000";
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constant SY_SY1 : std_logic_vector(3 downto 0) := "0001";
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constant SY_SY1 : std_logic_vector(3 downto 0) := "0001";
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constant SY_SY2 : std_logic_vector(3 downto 0) := "0010";
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constant SY_SY2 : std_logic_vector(3 downto 0) := "0010";
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constant SY_SY3 : std_logic_vector(3 downto 0) := "0011";
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constant SY_SY3 : std_logic_vector(3 downto 0) := "0011";
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constant SY_I16 : std_logic_vector(3 downto 0) := "0100";
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constant SY_I16 : std_logic_vector(3 downto 0) := "0100";
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constant SY_RR : std_logic_vector(3 downto 0) := "0101";
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constant SY_RR : std_logic_vector(3 downto 0) := "0101";
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constant SY_SI8 : std_logic_vector(3 downto 0) := "1000";
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constant SY_SI8 : std_logic_vector(3 downto 0) := "1000";
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constant SY_UI8 : std_logic_vector(3 downto 0) := "1001";
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constant SY_UI8 : std_logic_vector(3 downto 0) := "1001";
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constant SY_SQ : std_logic_vector(3 downto 0) := "1010";
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constant SY_SQ : std_logic_vector(3 downto 0) := "1010";
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constant SY_UQ : std_logic_vector(3 downto 0) := "1011";
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constant SY_UQ : std_logic_vector(3 downto 0) := "1011";
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constant SY_SM : std_logic_vector(3 downto 0) := "1100";
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constant SY_SM : std_logic_vector(3 downto 0) := "1100";
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constant SY_UM : std_logic_vector(3 downto 0) := "1101";
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constant SY_UM : std_logic_vector(3 downto 0) := "1101";
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constant SY_ANY : std_logic_vector(3 downto 0) := SY_RR;
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constant SY_ANY : std_logic_vector(3 downto 0) := SY_RR;
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--------------------------------------------------------------
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--------------------------------------------------------------
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constant PC_NEXT : std_logic_vector(2 downto 0) := "000"; -- count up
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constant PC_NEXT : std_logic_vector(2 downto 0) := "000"; -- count up
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constant PC_JMP : std_logic_vector(2 downto 0) := "001"; -- JMP/CALL
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constant PC_JMP : std_logic_vector(2 downto 0) := "001"; -- JMP/CALL
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constant PC_RETH : std_logic_vector(2 downto 0) := "010"; -- RET (H)
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constant PC_RETH : std_logic_vector(2 downto 0) := "010"; -- RET (H)
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constant PC_RETL : std_logic_vector(2 downto 0) := "011"; -- RET (L)
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constant PC_RETL : std_logic_vector(2 downto 0) := "011"; -- RET (L)
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constant PC_WAIT : std_logic_vector(2 downto 0) := "100"; -- WAIT
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constant PC_WAIT : std_logic_vector(2 downto 0) := "100"; -- WAIT
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constant PC_JPRR : std_logic_vector(2 downto 0) := "101"; -- JMP (RR)
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constant PC_JPRR : std_logic_vector(2 downto 0) := "101"; -- JMP (RR)
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constant PC_INT : std_logic_vector(2 downto 0) := "110"; -- INT
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constant PC_INT : std_logic_vector(2 downto 0) := "110"; -- INT
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--------------------------------------------------------------
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--------------------------------------------------------------
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end cpu_pack;
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end cpu_pack;
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package body cpu_pack is
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package body cpu_pack is
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end cpu_pack;
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end cpu_pack;
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