library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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entity DS1722 is
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entity DS1722 is
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Port( CLK_I: in std_logic;
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Port( CLK_I: in std_logic;
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RST_I: in std_logic;
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RST_I: in std_logic;
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DATA_IN: in std_logic_vector(7 downto 0);
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DATA_IN: in std_logic_vector(7 downto 0);
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DATA_OUT: out std_logic_vector(7 downto 0);
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DATA_OUT: out std_logic_vector(7 downto 0);
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ADDRESS: in std_logic_vector(7 downto 0);
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ADDRESS: in std_logic_vector(7 downto 0);
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START: in std_logic;
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START: in std_logic;
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DONE: out std_logic;
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DONE: out std_logic;
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TEMP_SPI: out STD_LOGIC; -- Physical interfaes
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TEMP_SPI: out STD_LOGIC; -- Physical interfaes
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TEMP_SPO: in STD_LOGIC;
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TEMP_SPO: in STD_LOGIC;
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TEMP_CE: out STD_LOGIC;
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TEMP_CE: out STD_LOGIC;
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TEMP_SCLK: out STD_LOGIC
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TEMP_SCLK: out STD_LOGIC
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);
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);
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end DS1722;
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end DS1722;
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architecture DS1722_arch of DS1722 is
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architecture DS1722_arch of DS1722 is
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signal counter : std_logic_vector(7 downto 0);
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signal counter : std_logic_vector(7 downto 0);
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signal data_latch : std_logic_vector(7 downto 0);
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signal data_latch : std_logic_vector(7 downto 0);
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type BIG_STATE is ( SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,
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type BIG_STATE is ( SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,
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DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,
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DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,
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NEXT_TO_LAST_ONE, LAST_ONE);
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NEXT_TO_LAST_ONE, LAST_ONE);
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signal state : BIG_STATE;
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signal state : BIG_STATE;
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signal bit_count: INTEGER range 0 to 7;
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signal bit_count: INTEGER range 0 to 7;
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signal Write: std_logic;
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signal Write: std_logic;
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begin
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begin
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-- divide CLK_I by 256
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-- divide CLK_I by 256
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--
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--
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process (CLK_I)
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process (CLK_I)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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if (RST_I = '1') then counter <= "00000000";
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if (RST_I = '1') then counter <= "00000000";
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else counter <= counter + "00000001";
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else counter <= counter + "00000001";
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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DONE <= START when (state = LAST_ONE) else '0';
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DONE <= START when (state = LAST_ONE) else '0';
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DATA_OUT <= data_latch;
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DATA_OUT <= data_latch;
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Write <= ADDRESS(7);
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Write <= ADDRESS(7);
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-- convert byte commands to SPI and SPI to byte.
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-- convert byte commands to SPI and SPI to byte.
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--
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--
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process (CLK_I)
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process (CLK_I)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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if (RST_I = '1') then
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if (RST_I = '1') then
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state <= SET_CE;
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state <= SET_CE;
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TEMP_CE <= '0';
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TEMP_CE <= '0';
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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bit_count <= 0;
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bit_count <= 0;
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elsif (counter = "11111111" and START = '1') then
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elsif (counter = "11111111" and START = '1') then
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case state is
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case state is
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when SET_CE =>
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when SET_CE =>
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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TEMP_CE <= '1';
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TEMP_CE <= '1';
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state <= LATCH_ADD;
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state <= LATCH_ADD;
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bit_count <= 0;
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bit_count <= 0;
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when LATCH_ADD =>
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when LATCH_ADD =>
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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TEMP_CE <= '1';
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TEMP_CE <= '1';
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state <= ADD_OUT_1;
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state <= ADD_OUT_1;
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data_latch <= ADDRESS;
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data_latch <= ADDRESS;
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when ADD_OUT_1 =>
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when ADD_OUT_1 =>
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TEMP_SCLK <= '1';
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TEMP_SCLK <= '1';
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TEMP_CE <= '1';
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TEMP_CE <= '1';
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state <= ADD_OUT_2;
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state <= ADD_OUT_2;
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TEMP_SPI <= data_latch(7);
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TEMP_SPI <= data_latch(7);
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when ADD_OUT_2 =>
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when ADD_OUT_2 =>
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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TEMP_CE <= '1';
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TEMP_CE <= '1';
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data_latch <= data_latch(6 downto 0) & data_latch(7);
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data_latch <= data_latch(6 downto 0) & data_latch(7);
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if bit_count < 7 then
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if bit_count < 7 then
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state <= ADD_OUT_1;
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state <= ADD_OUT_1;
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bit_count <= bit_count + 1;
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bit_count <= bit_count + 1;
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else
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else
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state <= DATA;
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state <= DATA;
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bit_count <= 0;
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bit_count <= 0;
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end if;
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end if;
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when DATA =>
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when DATA =>
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data_latch <= DATA_IN;
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data_latch <= DATA_IN;
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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TEMP_CE <= '1';
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TEMP_CE <= '1';
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if Write = '0' then
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if Write = '0' then
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state <= READ_DATA_1;
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state <= READ_DATA_1;
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else
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else
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state <= WRITE_DATA_1;
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state <= WRITE_DATA_1;
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end if;
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end if;
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when WRITE_DATA_1 =>
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when WRITE_DATA_1 =>
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TEMP_SCLK <= '1';
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TEMP_SCLK <= '1';
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TEMP_CE <= '1';
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TEMP_CE <= '1';
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state <= WRITE_DATA_2;
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state <= WRITE_DATA_2;
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TEMP_SPI <= data_latch(7);
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TEMP_SPI <= data_latch(7);
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when WRITE_DATA_2 =>
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when WRITE_DATA_2 =>
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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TEMP_CE <= '1';
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TEMP_CE <= '1';
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data_latch <= data_latch(6 downto 0) & data_latch(7);
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data_latch <= data_latch(6 downto 0) & data_latch(7);
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if bit_count < 7 then
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if bit_count < 7 then
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state <= WRITE_DATA_1;
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state <= WRITE_DATA_1;
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bit_count <= bit_count + 1;
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bit_count <= bit_count + 1;
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else
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else
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state <= NEXT_TO_LAST_ONE;
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state <= NEXT_TO_LAST_ONE;
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bit_count <= 0;
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bit_count <= 0;
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end if;
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end if;
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when READ_DATA_1 =>
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when READ_DATA_1 =>
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TEMP_SCLK <= '1';
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TEMP_SCLK <= '1';
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TEMP_CE <= '1';
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TEMP_CE <= '1';
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state <= READ_DATA_2;
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state <= READ_DATA_2;
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when READ_DATA_2 =>
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when READ_DATA_2 =>
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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TEMP_CE <= '1';
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TEMP_CE <= '1';
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data_latch <= data_latch(6 downto 0) & TEMP_SPO;
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data_latch <= data_latch(6 downto 0) & TEMP_SPO;
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if bit_count < 7 then
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if bit_count < 7 then
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state <= READ_DATA_1;
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state <= READ_DATA_1;
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bit_count <= bit_count + 1;
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bit_count <= bit_count + 1;
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else
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else
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state <= NEXT_TO_LAST_ONE;
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state <= NEXT_TO_LAST_ONE;
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bit_count <= 0;
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bit_count <= 0;
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end if;
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end if;
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when NEXT_TO_LAST_ONE =>
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when NEXT_TO_LAST_ONE =>
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TEMP_CE <= '0';
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TEMP_CE <= '0';
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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state <= LAST_ONE;
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state <= LAST_ONE;
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when LAST_ONE =>
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when LAST_ONE =>
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TEMP_CE <= '0';
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TEMP_CE <= '0';
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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state <= SET_CE;
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state <= SET_CE;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end DS1722_arch;
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end DS1722_arch;
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